Design and Analysis of FPGA Based 32 Bit ALU Using Reversible Gates

In this project, we are implementing a reversible ALU circuits in which convention irreversible gates are replaced using reversible logic gates. Here we are proposing reversible ALU circuit for addition operation. An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers .A 32-bit ALU was designed using reversible logical gates such as Peres gate, fredkin gate etc,. Which replaces the AND and OR for each one bit ALU circuit. The design here implemented can work fast than the ALU existing processor using less power. The design of an ALU and a Cache memory for use in a high performance processor was examined. Reversible logic vital in recent years because it has ability to reduce the power dissipation which is main requirement in low power design. This technique helps in reducing power consumption and power dissipation. This paper presents an implementation of ALU based on reversible logic while comparing it to an ALU architecture with the normal logic gates in terms of power consumption and delay leading to the improvement of performance of ALU circuit. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE 14.7.