Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

In this project, we are implementing a power-efficient design of the Wallace tree multiplier using a power efficient 7:3 counter consisting of multiplexer and ex-or gates. Recent development focuses on the design of low-power multiplier for applications like biomedical signal processing requiring the least power consumption and delay-tolerant multiplier. This paper proposes. The maximum power of the multiplier is consumed in the partial product tree reduction, and hence, in the proposed counter-based modular Wallace tree (CBMW) multiplier partial products are reduced using sequential 7:3 counter and the multi-bit addition in a single column reduces the complexity of the multiplier due to improvement in the locality. These proposed changes make design low power and scalable. The hardware utilization is minimum when a single 7:3 counter is used in partial product tree reduction per stage. With the advancement in technology, various designs of multipliers offering low power consumption, high speed and less area have been proposed by many researchers. The main concern of electronic system designers is the energy minimization with the minimum penalty in speed and area for designing portable devices.