Design of Low Power Magnitude Comparator

A low power two bit magnitude comparator has been proposed in the present work. The proposed magnitude comparator using the technology of coupling has been compared with the basic comparator circuit. The performance analysis of both the different comparators has been done for power consumption, delay and power delay-product (PDP) with VDD sweep. The simulations are carried on Mentor graphics (T-Spice) using 90nm CMOS technology at 1 V supply.