Design And Implementation of UART Based on Verilog HDL

This project focuses on designing and implementing a Universal Asynchronous Receiver/Transmitter (UART) communication protocol using Verilog HDL and testing it on an FPGA platform. UART is a simple yet widely adopted asynchronous serial communication protocol that transmits and receives data between devices using only two wires: a transmitter (TX) and a receiver (RX). In this project, a UART system is developed with two primary modules: a transmitter module, which converts parallel input data into serial output with start and stop framing, and a receiver module, which captures serial input, verifies it, and converts it back to parallel form. A baud rate generator is implemented to ensure that data is transmitted and received at the same predefined speed, enabling synchronization between the sender and receiver. The entire design is simulated and validated using a testbench, and real-time implementation is carried out on an FPGA board (e.g., Xilinx Artix-7). The project provides a foundation for digital communication systems, demonstrates the importance of reliable serial communication, and prepares for more advanced protocols like SPI, I2C, or CAN. This work finds applications in embedded systems, sensor communication, debugging interfaces, and FPGA-based communication systems, ensuring robust and efficient data transfer.

Keywords: Baud rate, Asynchronous Transmitter/Receiver, Finite State Machine (FSM),  Secure communication