Also Available Domains Arithmetic Core|Xilinx Vivado|Xilinx ISE
The aim of this project is to implement the high performance adders and multipliers by using Majority logic gates and the multipliers are designed using reduction circuitry like compressors.
Approximate computing deals with error tolerance in the computational process as a new paradigm for nano-scale technologies to improve performance and reduce power consumption. Majority logic (ML) is applicable to many emerging nanotechnologies. Its basic building block (3-input majority voting, MV) has been widely used for the design of digital circuits. Designs of approximate adder is evaluated in different complement bits depending on the size of the multiplier, an influence factor is defined and analyzed by a scheme for selecting the complement bits is also presented. The proposed designs will be evaluated using hardware metrics as well as error metrics. The expert compared to other ML-based models found in the technical literature Case studies of systems that are resistant to errors are also provided to illustrate the validity of the proposed models.
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