In this project, a hardware efficient architecture for Discrete Cosine Transform (DCT) was proposed. Design of less complexity computing hardware architecture for trigonometric and exponential has become challenge for many researchers. CORDIC algorithm has emerged in last decade to provide efficient computing for trigonometric, exponential and logarithmic computations. As the multimedia applications demand high speed and parallel computation of data, the CORDIC algorithm is a suitable computing technique to process such applications. The proposed architecture has been realized using verilog HDL and implemented to capture its design attributes such as speed and design complexity and compared with simple DCT architectures. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE 14.7\Xilinx Vivado.
Keywords:- FPGA, Discrete Cosine Transform, Hardware Architecture, CORDIC Processor, General Purpose Processor, Digital Signal Processor
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Software Requirements:
Hardware Requirements: