Carry select adder using BEC and RCA

In this we present a design of BEC based carry select adder. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The Carry select adder (CSLA) is used in many computational systems to lessen the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. In the proposed method we are implementing a carry select adder by using both BEC and RCA adder. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input, then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA to achieve high speed and low power consumption .The synthesis and simulation are verified by using Xilinx ISE 14.7 version tool.