Also Available Domains Transistor Logic|Cadence EDA
The main of this project is to reduce the delay and NBTI effects by using N-mos transistors in Schmitt trigger design
In this paper, a novel BTI resilient voltage bootstrapped Schmitt trigger (VB-ST) circuit with improved noise margin, leakage power and rail-to-rail voltage is proposed. An only NMOS transistor is used in the proposed VB-ST circuit, which helps to reduce the aging effect specially Negative Bias Temperature Instability (NBTI) on the circuit. Since output voltage swing is improved noise immunity is improved. And the proposed Schmitt trigger is tolerant to the effects of radiation hardened particles. The proposed Schmitt trigger was designed using 45nm Technology file using Tanner EDA tool with a supply voltage of 0.4V
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