Analysis of an Efficient Fault Tolerant Linear Feedback Shift Register for Low Power Applications

Abstract: 

The method of combining thousands of transistors into a single chip is known as VLSI. The primary purpose of VLSI design is to reduce the area of interconnecting fabrics. The LFSR is one of the most widely used sequence syllogisms since it gives a functional form from its previous state. The conventional LFSR is made up of memory blocks and XORs. The (LFSR) is the core of integrated devices that use patterns of randomly generated bits, such as digitalization clocks, created tests, and pseudo-random number and pseudo-noise sequence generators. For applications that need dependability, fault-tolerant LFSR development is therefore essential. A significant portion of conventional fault-tolerant LFSRs contain SPoFs, meaning that any mistake results in the project's complete failure. A unique fault-tolerant architecture for the single goal failure With a significantly reduced number of SPoFs, the Fault Tolerant-Linear Feedback Shift Register (FT-LFSR) has been designed. In order to differentiate the operating component, this work uses a novel form of Triple Modular Redundancy (TMR) with extra management components. The spatially redundant fault tolerance system known as TMR (Triple Modular Redundancy) was highly effective and popular. TMR's architecture makes it especially difficult to execute a process in parallel, after which the outcome is examined by a mechanism with the biggest group size to produce a single output. Consequently, the likelihood of single number failures is decreased in this recommended method. In addition to its limited SPoFs and other concurrent faults, Xilinx empirical investigations demonstrate that the FT-LFSR is impervious to all individual transient and persistent errors.

 Key Words——LSFR, VLSI, Xilinx suit, FT-LFSR