Paper PublishingAn Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic
Also Available Domains Xilinx Vivado
Objective
The main aim of this project is to reduce the area complexity of multiplier over the delay. This will be applicable when the design needs finite number of inputs and outputs in operation.
Abstract
Finite field multiplication is vastly uses in cryptographic circuits. As these finite field multiplications has great complications while building the circuits. So karatsuba algorithm is used to reduce the maximum amount of complexity by dividing each number into n/2 bit so the space complexity got even be reduced but the time complexity will increase as well. So in this paper we implement karatsuba-like multiplier but not completely karatsuba. We use both karatsuba and SBM (school book multiplication to reduce the amount of time complexity. Using both in a way will reduce the both complexity in a way. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier.
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Block Diagram
Specifications
Specifications:
Software Requirements:
Xilinx ISE
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
Learning Outcomes:
- Basics of Digital Electronics
- VLSI design Flow
- Knowledge in Cryptography.
- Advanced Encryption Scheme (AES) technique
- Data security
- Side channel attacks (SCA)
- Applications in real time
· Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation Skills
o Thesis Writing Skills
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