An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

Also Available Domains Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE297

Objective

In this project, a novel implementation of True Random Number Generator was designed with the help of the Digital Clock Manager blocks which is available in the FPGA.

Abstract

In modern cryptographic systems, True Random Number Generators (TRNGs) play avital role. Field Programmable Gate Arrays (FPGAs) form an ideal platform for hardware implementations of many of these security algorithms. In this paper we present a highly efficient and tunable TRNG based on the principle of Beat Frequency Detection (BFD), specifically for Xilinx FPGA based applications. The main advantages of the proposed TRNG are its on-the-fly tunability through Dynamic Partial Reconfiguration (DPR) to improve randomness qualities. The proposed TRNG has low hardware footprint and in-built bias elimination capabilities. The random bit streams generated from it passes all tests in the NIST statistical test suite.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram

Specifications

Software Requirements:

Xilinx ISE Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP,
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
FPGA design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Combinational & Sequential circuits
Knowledge on Arithmetic circuits
About SFD, DCM, Dynamic reconfiguration ports
Knowledge on true random number generator
About architecture of tuning circuit
Applications of tunable BFD-TRNG in real time
Xilinx ISE for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
Testing
DSP Core
Communications
Nano Technology

Back End Domains

Cadence EDA
Transistor Logic
Core Memories
Low Power VLSI

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice