An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology

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Project Code :TVPGTO904


The main aim of this project is to present a Low-Power Power-on-Reset circuit based on the reference of current.


In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. This entire schematic is simulated in Cadence Virtuoso employing GPDK 45nm library file.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram



Software Requirements:

·         Cadence Virtuoso

·         Technology files: GPDK 45nm

Hardware Requirements:

·         Microsoft® Windows XP

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

·         512 MB RAM

·         100 MB of available disk space

Learning Outcomes

Learning Outcomes:

  • Introduction to POR Circuit
  • Transistors & its applications

o   Types of Transistors

o   Logic Gates using Transistors

o   Pull Up and Pull Down networks

o   Importance of Transistors

  • MOS Fundamentals
  • NMOS/PMOS/CMOS Technologies
  • How to design circuits using Transistor logic?
  • Transistor level design for POR circuit.
  • Scope of  POR circuit in today’s world
  • Applications in real time
  • Cadence Virtuoso tool for design and simulation
  • Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation skills

o   Thesis Writing Skills

Demo Video

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