A 32-bit Integer Division Algorithm Based on Priority Encoder

Also Available Domains Communications|Xilinx Vivado|Xilinx ISE

Project Code :TVMAFE470

Abstract

In this project, an algorithm for 32-bit integer division is proposed. The algorithm calculates the integer division of positive and negative dividends and divisors represented in sign and magnitude. It calculates the magnitudes and signs of the quotient and remainder separately based on the magnitudes and signs of the divided and divisor. In the algorithm, the magnitude of the remainder is initially set to be the dividend and is iteratively reduced until it becomes smaller than the magnitude of the divisor; afterwards the algorithm converges. A priority encoder is used to improve the convergence rate by skipping the zeros between the high bits while shifting the divisor in each iteration to be aligned with the partial remainder. The magnitude of the quotient is initially set to zero and updated based on the amount of shift in each iteration. A hardware architecture is proposed to implement the algorithm.

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Block Diagram

Specifications

Software Requirements:

Xilinx Vivado Tool
HDL: Verilog

Hardware Requirements:

Microsoft® Windows XP
Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
512 MB RAM
100 MB of available disk space

Learning Outcomes

Basics of Digital Electronics
VLSI design Flow
Introduction to Verilog Coding
Different modeling styles in Verilog

Data Flow modeling
Structural modeling
Behavioral modeling
Mixed level modeling

Introduction to integer in binary representation
Knowledge on division operation
Different types of division algorithms
Knowledge on subtractions
Knowledge on barrel shifter & priority encoder
Applications in real time
Xilinx ISE 14.7/Xilinx Vivado for design and simulation
Generation of Netlist
Solution providing for real time problems
Project Development Skills:

Problem Analysis Skills
Problem Solving Skills
Logical Skills
Designing Skills
Testing Skills
Debugging Skills
Presentation Skills
Thesis Writing Skills

Demo Video

Front End Domains

Cadence EDA
Finite State Machines
Arithmetic Core
Testing
DSP Core
Communications
Nano Technology

Back End Domains

Cadence EDA
Transistor Logic
Core Memories
Low Power VLSI

Tools

FPGA
H-Spice
Cadence EDA
QCA
Xilinx Vivado
Xilinx ISE
Tanner EDA
LT-Spice

Others

Matlab Interfacing

H-Spice

LT-Spice