Also Available Domains Tanner EDA|Core Memories
The main objective of this project is to present a NVRAM TRNG using a novel mechanism to manage the charges into SFG.
True Random Number Generator (TRNG) provides the different keys for device authentication and cryptography. Typically, the TRNG is implemented in a standalone module into the systems, increasing the complexity and area of the implementation. In addition, the system needs to store the key generated by the TRNG in non-volatile memory for the different applications. However, implementing a Non-Volatile Random Access Memory (NVRAM) requires additional technology features, usually unavailable or expensive. This project presents a unified NVRAM-TRNG in a 45nm standard CMOS technology. The unified implementation does not need additional circuits for the random number generation mode. The differential NVRAM bit cell is implemented using a high voltage transistor to resist the non-volatile memory application. The proposed design has been simulated using the TANNER EDA 13.0 /CADENCE VIRTUOSO.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
o Types of Transistors
o Logic Gates using Transistors
o Pull Up and Pull Down networks
o Importance of Transistors
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