A Unified NVRAM and TRNG in Standard CMOS Technology

Also Available Domains Tanner EDA

Project Code :TVPGTO906


The main objective of this project is to present a NVRAM TRNG using a novel mechanism to manage the charges into SFG.

Block Diagram


Software Requirements:


·         Technology files: 45nm

Hardware Requirements:

·         Microsoft® Windows XP

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

·         512 MB RAM

·         100 MB of available disk space

Learning Outcomes

Learning Outcomes:

  • Introduction to NVRAM
  • Need of NVSRAM in IOT applications
  • Transistors & its applications

o   Types of Transistors

o   Logic Gates using Transistors

o   Pull Up and Pull Down networks

o   Importance of Transistors

  • MOS Fundamentals
  • NMOS/PMOS/CMOS Technologies
  • How to design circuits using Transistor logic?
  • Transistor level design for NVRAM
  • How to design low power, high speed area efficient transistor level circuits?
  • Drawbacks in CMOS technology
  • Scope of  NVRAM & Cryptography in today’s world
  • Applications in real time

·         CADENCE  VIRTUOSO  tool for design and simulation

  • Solution providing for real time problems

·         Project Development Skills:

o   Problem Analysis Skills

o   Problem Solving Skills

o   Logical Skills

o   Designing Skills

o   Testing Skills

o   Debugging Skills

o   Presentation skills

o   Thesis Writing Skills

Demo Video

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