A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application
Also Available Domains Tanner EDA|Cadence EDA|Low Power VLSI
Objective
The main aim of this project is to design master slave flip-flop using adaptive coupling techniques with minimum number of transistors in order to reduce power consumption.
Abstract
This paper presenting a different configuration of Flip-Flop with less number of transistor count. This structure depends on three configurations such as topological, logical and adaptive coupling techniques. This structure is designed using Complementary pass transistor logic. This novel design is simulated in TANNER EDA 13.0 /CADENCE VIRTUOSO employing GPDK library files.
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
Block Diagram
Specifications
Specifications:
Software Requirements:
· TANNER EDA 13.0 /CADENCE VIRTUOS
· Technology files: GPDK 45nm
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space
Learning Outcomes
- Introduction to FlipFlop
- Applications of Flipflops
- Different design styles in Flipflops
- Knowledge on CMOS Configurations
- Transmission Gate Logic
- Pass Transistor Logic
- Complementary PTL
- Transistors & its applications
o Types of Transistors
o Logic Gates using Transistors
o Pull Up and Pull Down networks
o Importance of Transistors
- MOS Fundamentals
- NMOS/PMOS/CMOS Technologies
- How to design circuits using Transistor logic?
- Transistor level design for FF.
- How to design low power, high speed area efficient transistor level circuits?
- Drawbacks in CMOS technology
- Scope of FF in today’s world
- Applications in real time
- TANNER EDA 13.0 /CADENCE VIRTUOSO tool for design and simulation
- Solution providing for real time problems
· Project Development Skills:
o Problem Analysis Skills
o Problem Solving Skills
o Logical Skills
o Designing Skills
o Testing Skills
o Debugging Skills
o Presentation skills
o Thesis Writing Skills
Related Projects
Paper Publishing
Request Call Back
Would you like to receive a free callback now?
Choose the best time for callback:
Leave your message and we will contact you as soon as possible
Disclaimer - Takeoff Edu Group Projects, are not associated or affiliated with IEEE, in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, and not projects of or by IEEE.
