This paper presents a new architecture for LFSR using gated clock approach. As it is well known that, clock gating approach is one among the low power techniques. Here this clock gating is also designed in a different configuration. There is a separate logic for the gated clock generation which is applied as a clock signal to the structure of LFSR. This complete architecture is designed and simulated using Tanner EDA/cadence employing respective library files.