A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers

Also Available Domains Tanner EDA|Cadence EDA|LT-Spice|Low Power VLSI

Project Code :TVMABE197


The main objective of this project is to reduce the power consumption of LFSR using gated clock approach.


This paper presents a new architecture for LFSR using gated clock approach. As it is well known that, clock gating approach is one among the low power techniques. Here this clock gating is also designed in a different configuration. There is a separate logic for the gated clock generation which is applied as a clock signal to the structure of LFSR. This complete architecture is designed and simulated using Tanner EDA/cadence employing respective library files.

NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.

Block Diagram



Software Requirements:

·         Cadence/Tanner tool

·         Technology files: 45nm

Hardware Requirements:

·         Microsoft® Windows XP

·         Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

·         512 MB RAM

·         100 MB of available disk space


Demo Video

Request Video

Related Projects

Final year projects