A Novel Approximate Adder Design using Error Reduced Carry Prediction and Constant Truncation

Also Available Domains Arithmetic Core|Xilinx Vivado

Project Code :TVPGTO617

Objective

The main aim of this paper is to improve the computation accuracy while providing excellent hardware efficiency. This paper presents approximate adder design using Carry prediction logic and constant truncation.

Abstract

This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. The proposed carry prediction technique can reduce a prediction error rate compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). An excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.

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Block Diagram

Specifications

Software Requirements:

  • Xilinx ISE 14.7 Tool 
  • HDL: Verilog

Hardware Requirements:

  • Microsoft® Windows XP
  • Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support 
  • 512 MB RAM
  • 100 MB of available disk space

Learning Outcomes

  • Basics of Digital Electronics
  • VLSI design Flow
  • Introduction to Verilog Coding
  • Different modeling styles in Verilog
    • Data Flow modeling
    • Structural modeling
    • Behavioral modeling
    • Mixed level modeling
  • Introduction to Arithmetic circuits
  • Knowledge on types of approximate adder circuits
  • Different approximation techniques
  • Knowledge on approximate FA adder designs 
  • Applications in real time
  • Xilinx ISE 14.7 for design and simulation
  • Generation of Netlist
  • Solution providing for real time problems
  • Project Development Skills:
    • Problem Analysis Skills
    • Problem Solving Skills
    • Logical Skills
    • Designing Skills
    • Testing Skills
    • Debugging Skills
    • Presentation Skills
    • Thesis Writing Skills

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