A Novel Approximate Adder Design using Error Reduced Carry Prediction and Constant Truncation

This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing excellent hardware efficiency. The proposed carry prediction technique can reduce a prediction error rate compared to existing approximate adders considered in this paper. Furthermore, the error reduction technique also enhances the overall computation accuracy by decreasing the error distance (ED). An excellent design tradeoff allows the proposed adder to be the most competitive of the adders under consideration. Furthermore, we confirm that the approximation errors caused by the proposed adder have very little impact on output quality when adopted in practical applications, such as digital image processing and machine learning.