A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator against Side-Channel Attacks

Data Security is considered to be a major factor and plays an important role in most of the applications such as e-commerce, internet banking, military, satellite, wireless communications, electronic gadgets, appliances, signal and digital image processing, etc. Cryptography is a technique which is used to keep the data safe and secret by changing it into a form so that unnecessary users cannot understand. This technique provides a strong, economical way to keep our data as a secret and helps in data integrity verification. Cryptography technique is facing issue from side channel attacks and unable to provide error free data. The proposed AES accelerator achieves vertical (amplitude) SCA hiding via an area-efficient dual-rail mapping approach and a zero-value (ZV) compensated substitution-box (S-Box), while enhancing the horizontal (temporal) SCA hiding of asynchronous logic operations via a timing-boundary-free input arrival time randomizer and a skewed-delay controller. This design will decrease the area overhead and provide strong resistance from side channel attacks. The proposed design is executed in Xilinx ISE 14.7 and the output is verified using simulation results.