Also Available Domains DSP Core|Xilinx Vivado
The main objective of this project is to implement a MAC architecture with Low power & reduced delay. The MAC unit was designed with mainly partial product generation and Accumulation units. Hence the delay can be reduced by integrating a part of additions into the partial product reduction (PPR) process
In this project, we propose low-power high-speed pipelined Mac architecture. Carry propagation of additions consume more power and large path-delay, to resolve this problem we introduce a proposed method. In this we integrate a part of additions into a partial product reduction process. Until the PPR process of next multiplication, addition and accumulation of MSB bits are not performed.
To correctly contrast with surplus in the PPR process, a small size adder is designed to accumulate the total number of carries. The effectiveness of the proposed method is designed using XilinxISE14.7
Keywords: MAC unit, dadda multiplier, Arithmetic circuits, alpha-bit adder
NOTE: Without the concern of our team, please don't submit to the college. This Abstract varies based on student requirements.
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