Also Available Domains DSP Core|Cadence EDA|Xilinx Vivado
The main objective of this paper is to enhance the operation speed with the help of instruction set architecture. The multiplier and dividers are employed to perform both signed and unsigned operations with less area cost
In this project a high performance micro architecture based on RISC-V ISA has been proposed. Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. In this brief, a novel processor micro-architecture is designed which is capable of achieving these requirements. This micro architecture is based on RISC-V Instruction Set Architecture (ISA). The proposed RISC V proposed here is a four stage pipeline architecture with very basic components to get the best possible result. This design consumes a dynamic power which is better than ARM Cortex-M3 and Cortex-M4 and also lower than many others designs. The results show that this core can outperform many existing commercial and open-source cores. The effectiveness of the proposed method is synthesized and simulated using Xilinx ISE14.7.
Keywords: - Micro-architecture, RV32IM, RISC-V, functional unit, Baugh Wooley, Booth, vedic, Dadda, FPGA, ARM.
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