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This paper presents the 4-bit vedic multiplier using CMOS and MGDI Techniques. Here, the 4-bit vedic multiplier is designed using 2-bit vedic multipliers, Ripple Carry Adders and a Half Adder.
Abstract: In this paper, a 4 bit Vedic multiplier is designed using CMOS technology and MGDI technique. The performance of the system basically works better if the performance of the multiplier is good. In today's digital time, Multiplier is one which consumes power at the same time speed of multiplier is playing very important aspects in this. Multiplier Optimization for power and delay both will play an important role. Adders are also play an important role in the multiplier. Here, we are using Ripple carry adder. In this project, the design is implemented using Cadence Virtuoso tool/Tanner EDA Tool employing gpdk 90nm technology. In this, we perform transient results along with parameters of Area, Delay and maximum power.
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Software Requirements:
· Cadence Virtuoso/Tanner Tool
· Technology files: gpdk 90nm
Hardware Requirements:
· Microsoft® Windows XP
· Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support
· 512 MB RAM
· 100 MB of available disk space