Project Code: TVMAFE567
Project Title:Area Reduction AES Algorithm in Hardware Trojan DetectionView DetailsProject Code: TVMAFE580
Project Title:Area-Efficient LFSR-Based Stochastic Number Generators with Minimum CorrelationView DetailsProject Code: TVMAFE584
Project Title:Implementation of Delayed LMS algorithm based Adaptive filter using Verilog HDLView DetailsProject Code: TVMAFE588
Project Title:Design of a VLSI Router for the Faster Data Transmission Using BufferView DetailsProject Code: TVMAFE589
Project Title:High Performance VLSI Architecture of FIR Filter for Seismic Signal ProcessingView DetailsProject Code: TVMAFE601
Project Title:Design And Implementation of UART Based on Verilog HDLView DetailsProject Code: TVMAFE602
Project Title:An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient ApplicationsView DetailsProject Code: TVMAFE603
Project Title:A Lightweight True Random Number Generator for Root of Trust ApplicationsView DetailsProject Code: TVMAFE604
Project Title:Design of Implicit Partial Product-LDPC Codes and Low Complexity Decoding AlgorithmView Details Items per page:
1 – 10 of 10
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVMAFE567 | Area Reduction AES Algorithm in Hardware Trojan Detection | |
| 2 | TVMAFE580 | Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Co... | |
| 3 | TVMAFE584 | Implementation of Delayed LMS algorithm based Adaptive filter using Ve... | |
| 4 | TVMAFE585 | AxPPA Approximate Parallel Prefix Adders | |
| 5 | TVMAFE588 | Design of a VLSI Router for the Faster Data Transmission Using Buffer | |
| 6 | TVMAFE589 | High Performance VLSI Architecture of FIR Filter for Seismic Signal P... | |
| 7 | TVMAFE601 | Design And Implementation of UART Based on Verilog HDL | |
| 8 | TVMAFE602 | An Ultra-Efficient Approximate Multiplier With Error Compensation for ... | |
| 9 | TVMAFE603 | A Lightweight True Random Number Generator for Root of Trust Applicati... | |
| 10 | TVMAFE604 | Design of Implicit Partial Product-LDPC Codes and Low Complexity Decod... |
Items per page:
1 – 10 of 10
Project Code: TVMAFE567
Project Title:Area Reduction AES Algorithm in Hardware Trojan DetectionView DetailsProject Code: TVMAFE580
Project Title:Area-Efficient LFSR-Based Stochastic Number Generators with Minimum CorrelationView DetailsProject Code: TVMAFE584
Project Title:Implementation of Delayed LMS algorithm based Adaptive filter using Verilog HDLView DetailsProject Code: TVMAFE588
Project Title:Design of a VLSI Router for the Faster Data Transmission Using BufferView DetailsProject Code: TVMAFE589
Project Title:High Performance VLSI Architecture of FIR Filter for Seismic Signal ProcessingView DetailsProject Code: TVMAFE601
Project Title:Design And Implementation of UART Based on Verilog HDLView DetailsProject Code: TVMAFE602
Project Title:An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient ApplicationsView DetailsProject Code: TVMAFE603
Project Title:A Lightweight True Random Number Generator for Root of Trust ApplicationsView DetailsProject Code: TVMAFE604
Project Title:Design of Implicit Partial Product-LDPC Codes and Low Complexity Decoding AlgorithmView Details Items per page:
1 – 10 of 10
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVMAFE567 | Area Reduction AES Algorithm in Hardware Trojan Detection | |
| 2 | TVMAFE580 | Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Co... | |
| 3 | TVMAFE584 | Implementation of Delayed LMS algorithm based Adaptive filter using Ve... | |
| 4 | TVMAFE585 | AxPPA Approximate Parallel Prefix Adders | |
| 5 | TVMAFE588 | Design of a VLSI Router for the Faster Data Transmission Using Buffer | |
| 6 | TVMAFE589 | High Performance VLSI Architecture of FIR Filter for Seismic Signal P... | |
| 7 | TVMAFE601 | Design And Implementation of UART Based on Verilog HDL | |
| 8 | TVMAFE602 | An Ultra-Efficient Approximate Multiplier With Error Compensation for ... | |
| 9 | TVMAFE603 | A Lightweight True Random Number Generator for Root of Trust Applicati... | |
| 10 | TVMAFE604 | Design of Implicit Partial Product-LDPC Codes and Low Complexity Decod... |
Items per page:
1 – 10 of 10
Project Code: TVMAFE567
Project Title:Area Reduction AES Algorithm in Hardware Trojan DetectionView DetailsProject Code: TVMAFE580
Project Title:Area-Efficient LFSR-Based Stochastic Number Generators with Minimum CorrelationView DetailsProject Code: TVMAFE584
Project Title:Implementation of Delayed LMS algorithm based Adaptive filter using Verilog HDLView DetailsProject Code: TVMAFE588
Project Title:Design of a VLSI Router for the Faster Data Transmission Using BufferView DetailsProject Code: TVMAFE589
Project Title:High Performance VLSI Architecture of FIR Filter for Seismic Signal ProcessingView DetailsProject Code: TVMAFE601
Project Title:Design And Implementation of UART Based on Verilog HDLView DetailsProject Code: TVMAFE602
Project Title:An Ultra-Efficient Approximate Multiplier With Error Compensation for Error-Resilient ApplicationsView DetailsProject Code: TVMAFE603
Project Title:A Lightweight True Random Number Generator for Root of Trust ApplicationsView DetailsProject Code: TVMAFE604
Project Title:Design of Implicit Partial Product-LDPC Codes and Low Complexity Decoding AlgorithmView Details Items per page:
1 – 10 of 10
S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVMAFE567 | Area Reduction AES Algorithm in Hardware Trojan Detection | |
| 2 | TVMAFE580 | Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Co... | |
| 3 | TVMAFE584 | Implementation of Delayed LMS algorithm based Adaptive filter using Ve... | |
| 4 | TVMAFE585 | AxPPA Approximate Parallel Prefix Adders | |
| 5 | TVMAFE588 | Design of a VLSI Router for the Faster Data Transmission Using Buffer | |
| 6 | TVMAFE589 | High Performance VLSI Architecture of FIR Filter for Seismic Signal P... | |
| 7 | TVMAFE601 | Design And Implementation of UART Based on Verilog HDL | |
| 8 | TVMAFE602 | An Ultra-Efficient Approximate Multiplier With Error Compensation for ... | |
| 9 | TVMAFE603 | A Lightweight True Random Number Generator for Root of Trust Applicati... | |
| 10 | TVMAFE604 | Design of Implicit Partial Product-LDPC Codes and Low Complexity Decod... |
Items per page:
1 – 10 of 10
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Disclaimer - Takeoff Edu Group Projects, are not associated or affiliated with IEEE, in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, and not projects of or by IEEE.
