S.no
Project Code
Project Name
Action
1 TVMAFE604 Design of Implicit Partial Product-LDPC Codes and Low Complexity Decod...
2 TVMAFE603 A Lightweight True Random Number Generator for Root of Trust Applicati...
3 TVMAFE602 An Ultra-Efficient Approximate Multiplier With Error Compensation for ...
4 TVMAFE601 Design And Implementation of UART Based on Verilog HDL
5 TVMAFE589 High Performance VLSI Architecture of FIR Filter for Seismic Signal P...
6 TVMAFE588 Design of a VLSI Router for the Faster Data Transmission Using Buffer
7 TVMAFE585 AxPPA Approximate Parallel Prefix Adders
8 TVMAFE584 Implementation of Delayed LMS algorithm based Adaptive filter using Ve...
9 TVMAFE580 Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Co...
10 TVMAFE567 Area Reduction AES Algorithm in Hardware Trojan Detection
Items per page:
1 – 10 of 10
S.no
Project Code
Project Name
Action
1 TVMAFE604 Design of Implicit Partial Product-LDPC Codes and Low Complexity Decod...
2 TVMAFE603 A Lightweight True Random Number Generator for Root of Trust Applicati...
3 TVMAFE602 An Ultra-Efficient Approximate Multiplier With Error Compensation for ...
4 TVMAFE601 Design And Implementation of UART Based on Verilog HDL
5 TVMAFE589 High Performance VLSI Architecture of FIR Filter for Seismic Signal P...
6 TVMAFE588 Design of a VLSI Router for the Faster Data Transmission Using Buffer
7 TVMAFE585 AxPPA Approximate Parallel Prefix Adders
8 TVMAFE584 Implementation of Delayed LMS algorithm based Adaptive filter using Ve...
9 TVMAFE580 Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Co...
10 TVMAFE567 Area Reduction AES Algorithm in Hardware Trojan Detection
Items per page:
1 – 10 of 10
S.no
Project Code
Project Name
Action
1 TVMAFE604 Design of Implicit Partial Product-LDPC Codes and Low Complexity Decod...
2 TVMAFE603 A Lightweight True Random Number Generator for Root of Trust Applicati...
3 TVMAFE602 An Ultra-Efficient Approximate Multiplier With Error Compensation for ...
4 TVMAFE601 Design And Implementation of UART Based on Verilog HDL
5 TVMAFE589 High Performance VLSI Architecture of FIR Filter for Seismic Signal P...
6 TVMAFE588 Design of a VLSI Router for the Faster Data Transmission Using Buffer
7 TVMAFE585 AxPPA Approximate Parallel Prefix Adders
8 TVMAFE584 Implementation of Delayed LMS algorithm based Adaptive filter using Ve...
9 TVMAFE580 Area-Efficient LFSR-Based Stochastic Number Generators with Minimum Co...
10 TVMAFE567 Area Reduction AES Algorithm in Hardware Trojan Detection
Items per page:
1 – 10 of 10

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