Items per page:
1 – 10 of 14
S.no
Project Code
Project Name
Action
1 TVPGFE325 The Constant Multiplier FFT

Xilinx Vivado|Xilinx ISE

2 TVPGFE324 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

Xilinx Vivado|Xilinx ISE|FPGA

3 TVPGFE322 Design and Implementation of Arbitrary Point FFT Based on RISC-V SoC

Xilinx Vivado|Xilinx ISE

4 TVPGFE321 Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI ...

Xilinx Vivado|Xilinx ISE

5 TVPGFE320 A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized ...

Xilinx Vivado|Xilinx ISE

6 TVPGFE302 A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low...

Cadence EDA|Xilinx Vivado|Xilinx ISE

7 TVPGFE305 Design and Verification of 16 bit RISC Processor Using Vedic Mathemati...

Xilinx Vivado|Xilinx ISE

8 TVPGFE307 Design of Very High-Speed Pipeline FIR Filter Through Precise Critical...

Xilinx Vivado|Xilinx ISE

9 TVPGFE296 An Efficient Modified Distributed Arithmetic Architecture Suitable for...

Xilinx Vivado|Xilinx ISE

10 TVPGFE295 Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Process...

Xilinx Vivado|Xilinx ISE

Items per page:
1 – 10 of 14
Items per page:
1 – 10 of 14
S.no
Project Code
Project Name
Action
1 TVPGFE325 The Constant Multiplier FFT

Xilinx Vivado|Xilinx ISE

2 TVPGFE324 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

Xilinx Vivado|Xilinx ISE|FPGA

3 TVPGFE322 Design and Implementation of Arbitrary Point FFT Based on RISC-V SoC

Xilinx Vivado|Xilinx ISE

4 TVPGFE321 Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI ...

Xilinx Vivado|Xilinx ISE

5 TVPGFE320 A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized ...

Xilinx Vivado|Xilinx ISE

6 TVPGFE302 A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low...

Cadence EDA|Xilinx Vivado|Xilinx ISE

7 TVPGFE305 Design and Verification of 16 bit RISC Processor Using Vedic Mathemati...

Xilinx Vivado|Xilinx ISE

8 TVPGFE307 Design of Very High-Speed Pipeline FIR Filter Through Precise Critical...

Xilinx Vivado|Xilinx ISE

9 TVPGFE296 An Efficient Modified Distributed Arithmetic Architecture Suitable for...

Xilinx Vivado|Xilinx ISE

10 TVPGFE295 Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Process...

Xilinx Vivado|Xilinx ISE

Items per page:
1 – 10 of 14
Items per page:
1 – 10 of 14
S.no
Project Code
Project Name
Action
1 TVPGFE325 The Constant Multiplier FFT

Xilinx Vivado|Xilinx ISE

2 TVPGFE324 MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapp...

Xilinx Vivado|Xilinx ISE|FPGA

3 TVPGFE322 Design and Implementation of Arbitrary Point FFT Based on RISC-V SoC

Xilinx Vivado|Xilinx ISE

4 TVPGFE321 Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI ...

Xilinx Vivado|Xilinx ISE

5 TVPGFE320 A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized ...

Xilinx Vivado|Xilinx ISE

6 TVPGFE302 A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low...

Cadence EDA|Xilinx Vivado|Xilinx ISE

7 TVPGFE305 Design and Verification of 16 bit RISC Processor Using Vedic Mathemati...

Xilinx Vivado|Xilinx ISE

8 TVPGFE307 Design of Very High-Speed Pipeline FIR Filter Through Precise Critical...

Xilinx Vivado|Xilinx ISE

9 TVPGFE296 An Efficient Modified Distributed Arithmetic Architecture Suitable for...

Xilinx Vivado|Xilinx ISE

10 TVPGFE295 Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Process...

Xilinx Vivado|Xilinx ISE

Items per page:
1 – 10 of 14
Final year projects