Paper PublishingProject Code: TVPGFE302
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsCadence EDA| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO589
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO590
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Cadence EDA| Xilinx ISE
View DetailsProject Code: TVPGTO591
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Cadence EDA| Xilinx Vivado
View DetailsProject Code: TVPGFE303
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodView DetailsProject Code: TVPGTO592
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodDesign for Testability| Xilinx ISE
View DetailsProject Code: TVPGTO593
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodDesign for Testability| Xilinx Vivado
View DetailsProject Code: TVPGFE304
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorView DetailsProject Code: TVPGTO594
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorView DetailsProject Code: TVPGTO595
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorArithmetic Core| Xilinx Vivado
View Details S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVPGFE302 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 2 | TVPGTO589 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 3 | TVPGTO590 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 4 | TVPGTO591 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 5 | TVPGFE303 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 6 | TVPGTO592 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 7 | TVPGTO593 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 8 | TVPGFE304 | Design and Analysis of Approximate Compressors for Balanced Error Accu... | |
| 9 | TVPGTO594 | Design and Analysis of Approximate Compressors for Balanced Error Accu... | |
| 10 | TVPGTO595 | Design and Analysis of Approximate Compressors for Balanced Error Accu... |
Project Code: TVPGFE302
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsCadence EDA| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO589
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO590
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Cadence EDA| Xilinx ISE
View DetailsProject Code: TVPGTO591
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Cadence EDA| Xilinx Vivado
View DetailsProject Code: TVPGFE303
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodView DetailsProject Code: TVPGTO592
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodDesign for Testability| Xilinx ISE
View DetailsProject Code: TVPGTO593
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodDesign for Testability| Xilinx Vivado
View DetailsProject Code: TVPGFE304
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorView DetailsProject Code: TVPGTO594
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorView DetailsProject Code: TVPGTO595
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorArithmetic Core| Xilinx Vivado
View Details S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVPGFE302 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 2 | TVPGTO589 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 3 | TVPGTO590 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 4 | TVPGTO591 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 5 | TVPGFE303 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 6 | TVPGTO592 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 7 | TVPGTO593 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 8 | TVPGFE304 | Design and Analysis of Approximate Compressors for Balanced Error Accu... | |
| 9 | TVPGTO594 | Design and Analysis of Approximate Compressors for Balanced Error Accu... | |
| 10 | TVPGTO595 | Design and Analysis of Approximate Compressors for Balanced Error Accu... |
Project Code: TVPGFE302
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsCadence EDA| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO589
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Xilinx Vivado| Xilinx ISE
View DetailsProject Code: TVPGTO590
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Cadence EDA| Xilinx ISE
View DetailsProject Code: TVPGTO591
Project Title:A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power ApplicationsDSP Core| Cadence EDA| Xilinx Vivado
View DetailsProject Code: TVPGFE303
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodView DetailsProject Code: TVPGTO592
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodDesign for Testability| Xilinx ISE
View DetailsProject Code: TVPGTO593
Project Title:Constant-time Synchronous Binary Counter with Minimal Clock PeriodDesign for Testability| Xilinx Vivado
View DetailsProject Code: TVPGFE304
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorView DetailsProject Code: TVPGTO594
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorView DetailsProject Code: TVPGTO595
Project Title:Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC OperatorArithmetic Core| Xilinx Vivado
View Details S.no | Project Code | Project Name | Action |
|---|---|---|---|
| 1 | TVPGFE302 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 2 | TVPGTO589 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 3 | TVPGTO590 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 4 | TVPGTO591 | A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low... | |
| 5 | TVPGFE303 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 6 | TVPGTO592 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 7 | TVPGTO593 | Constant-time Synchronous Binary Counter with Minimal Clock Period | |
| 8 | TVPGFE304 | Design and Analysis of Approximate Compressors for Balanced Error Accu... | |
| 9 | TVPGTO594 | Design and Analysis of Approximate Compressors for Balanced Error Accu... | |
| 10 | TVPGTO595 | Design and Analysis of Approximate Compressors for Balanced Error Accu... |
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Disclaimer - Takeoff Edu Group Projects, are not associated or affiliated with IEEE, in any way. The IEEE Projects mentioned here are mentioned in the context of student projects, whose ideas are derived from IEEE publications, and not projects of or by IEEE.
