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Vlsi Tanner EDA Projects For Mtech Students

Final year Mtech Vlsi Tanner EDA Projects.Get the list of Vlsi Tanner EDA Projects for Mtech.We will give guidelines about the projects,so students will get the real time knowledge and how to do the projects in a correct manner

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1 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression
2 A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA
3 CMCS: Current-Mode Clock Synthesis
4 Binary Adder Circuit Design Using Emerging MIGFET Devices
5 A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier
6 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
7 Delay Analysis for Current Mode Threshold Logic Gate Designs
8 A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar
9 A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies
10 A Memristor Based Binary Multiplier
11 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
12 Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays
13 Design and Low Power Magnitude Comparator
14 Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
15 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
16 High Performance Ternary Adder using CNTFET
17 High-performance engineered gate transistor-based compact digital circuits
18 Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
19 Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits
20 Optimized Memristor-Based Multipliers
21 Probability-Driven Multibit Flip-Flop Integration With Clock Gating
22 Register – Less NULL Conventional Logic
23 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
24 Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
25 Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
26 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
27 Fault Tolerant Logic Cell FPGA
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1 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
2 A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All- Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
3 A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
4 A Systematic Design Methodology of Asynchronous SAR ADCs
5 Read Bit line Sensing and Fast Local Write-Back Techniques in Hierarchical Bit line Architecture for Ultralow-Voltage SRAMs
6 Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs
7 Incorporating Process Variations Into SRAM Electro migration Reliability Assessment Using Atomic Flux Divergence
8 A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM
9 Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization
10 SRAM-Based Unique Chip Identifier Techniques
11 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
12 EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
13 Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits
14 Integrated Floating-Gate Programming Environment for System-Level ICs
15 PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
16 Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry
17 Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
18 An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
19 Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
20 Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
21 A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications
22 Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
23 Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology
24 Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents
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1 Voltage mode implementation of highly accurate analog multiplier circuit
2 Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme
3 Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing
4 Digtial to time converter using SET
5 Design of high speed ternary full adder and threeinput XOR circuits using CNTFETs
6 Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates
7 Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata
8 Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell
9 A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process
10 A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
11 A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology
12 A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links
13 A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique
14 An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells
15 Read Performance The Newest Barrier in Scaled STT-RAM
16 On the Nonvolatile Performance of Flip-FlopSRAM Cells With a Single MTJ
17 High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors
18 High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis
19 Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model
20 A CMOS PWM Transceiver Using Self-Referenced Edge Detection
1 Area Delay Power Efficient Carry Select Adder
2 On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
3 Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
4 A Method to Extend Orthogonal Latin Square Codes
5 Design and Estimation of delay power and area for Parallel prefix adders
6 Design and FPGA implementation of compressor based Vedic multiplier
7 A Combined SDC SDF Architecture for Normal I/O Pipelined Radix-2 FFT
8 Area Delay Efficient Binary Adders in QCA
9 Test Versus Security Past and Present
10 Skewed Load Test Cubes Based on Functional Broadside Tests for a Low Power Test Set
11 High Speed Convolution and De convolution Algorithm
12 Fast Radix 10 Multiplication Using Redundant BCD Codes
13 Low Complexity Low Latency Architecture for Matching of Data Encoded With Hard Systematic Error Correcting Codes
14 Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing
15 Design of High Performance 64 bit MAC Unit
16 Thwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison
17 Low Power Test Generation by Merging of Functional Broadside Test Cubes
18 Design of Dedicated Reversible Quantum Circuitry for Square Computation
19 A Look Ahead Clock Gating Based on Auto Gated Flip Flops
20 A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)
21 Aging Aware Reliable Multiplier Design With Adaptive Hold Logic
22 An Accuracy Adjustment Fixed Width Booth Multiplier Based on Multilevel Conditional Probability
23 Arithmetic Based Binary to RNS Converter Modulo {2n ± k} for jn-Bit Dynamic Range
24 Critical Path Analysis and Low Complexity Implementation of the LMS Adaptive Algorithm
25 Design Flow for Flip Flop Grouping in Data Driven Clock Gating
26 Design of Efficient Binary Comparators in Quantum Dot Cellular Automata
27 Efficient Hardware Implementation of Encoder and Decoder for Golay Code
28 Efficient Integer DCT Architectures for HEVC
29 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}
30 Fault Tolerant Parallel Filters Based on Error Correction Codes
31 Low Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure
32 On the Design of Efficient Modulo 2n+1 Multiply Add Add Units
33 Reverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations
34 FPGA based partial reconfigurable fir filter design
35 An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC
1 Thwarting Scan Based Attacks on Secure ICs With On Chip Comparison
2 Design for testablity support for launch and capture power reduction in launch of shift and launch of capture testing
3 Area Delay Efficient Binary Adders in QCA
4 CMOS Charge Pump With No Reversion Loss and Enhanced Drivability
5 Efficent Register renaming and recovery for high performance Processors
6 Low Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple
7 Enhanced memory reliabilty against multiple cells upsets using decimal
8 Average 8T Differential Sensing Subthreshold SRAM With Bit Interleaving
9 Reliable Concurrent Error Detection Architectures for Extended Euclidean
10 CORDIC Designs for Fixed Angle of Rotation
11 A Built In Repair Analyzer With Optimal Repair Rate for Word Oriented
12 Built In Generation of Functional Broadside Tests Using a Fixed Hardware
13 A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless
14 Design and Implementation of an On Chip Permutation Network for Multiprocessor
15 Glitch Free NAND Based Digitally Controlled Delay Lines
16 Computing Two Pattern Test Cubes for Transition Path Delay Faults
17 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density
18 A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture
19 Achieving High Performance On Chip Networks With Shared Buffer Routers
20 Analysis and Design of a Low Voltage Low Power Double Tail Comparator
21 Area Delay Power Efficient Fixed Point LMS Adaptive Filter With Low Adaptation
22 Comparative Study of Various Latch Type Sense Amplifiers
23 Delay Test for Diagnosis of Power Switches
24 Design of a Low Voltage Low Dropout Regulator
25 High resolution all digital duty cycle corrector in65nm cmos technology
26 Incremental Trace Buffer Insertion for FPGA Debug
27 Low Power Digital Signal Processor Architecture for Wireless Sensor Nodes
28 Memory Footprint Reduction for Power Efficient Realization of 2D Finite
29 On Chip Memory Hierarchy in One coarse grained reconfigurable architecture
30 On the Field Test and Configuration Infrastructure for 2D Mesh NoCs
31 Software Hardware Parallel Long Period Random Number Generation
32 Parasitics Aware Design of Symmetric and Asymmetric Gate Work function
33 Power Efficient Class AB Op Amps With High and symmetric slew rate
34 A Novel Modulo Adder for Residue Number System
35 Restoration Based Procedures With Set Covering Heuristics for Static Test
36 Smart Reliable Network on Chip
37 Test Compaction by Sharing of Transparent Scan Sequences Among Logic blocks
38 Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
39 Variation Aware Variable Latency Design
40 An Efficient Interpolation Based Chase BCH decoder
41 Energy efficient code converters by using reversible logic gates
42 An efficient SQRT architecture of Carry Select adder design by Boolean
43 An efficient high speed Wallace tree multiplier
44 Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA
45 Design of High Efficiency Carry Select Adder Using SQRT Technique
46 FPGA based implementation of a double precision IEEE floating point adder
47 LFSR reseeding scheme for achieving test coverage
48 Optimized architecture for Floating Point computation Unit
49 Radix 4 and Radix 8 Booth Encoded Multi Modulus Multipliers
50 Sharing Logic for Built In Generation of Functional Broadside
51 Implementation of cryptographic algorithm on FPGA
52 128 bit carry select adder having less area and delay
53 FPGA implementation high speed vedic multiplier using barrel shifter
54 Improved Design of Low Power TPG Using LPLFSR
55 HICPA 64 bit hybrid low power adder for high performance processors
56 128 bit low power VLSI adder subsystem
57 Parity preserving logic based fault tolerant reversible ALU
58 Efficient concurrent BIST with comparator based response analayzer
59 Area efficient high speed low power multiplier architecture for multirate filter design
60 Used self controllable voltage level techniques to reduce leakage currents
61 Minimization leakage current of full adder using deep sub micron CMOS
62 Normaliation of floating point multiplication using verilog hdl
63 Design and implementation of truncated multipliers for precision improvement
64 Design of high speed hardware efficient 4 bit sfq multiplier
65 VHdl implementation of non restoring division algorithem using high speed
66 Implementation of fixed point square root algorithem on fpga hardware
67 Platform independent customizable UART soft core
68 Design and Implementation of FPGA based High Resolution Digital Pulse
69 Design and implementation of floating point ALU in FPGA
70 Hardware implementation of truncated multiplier based on multiplier
71 Time multiplexed offset carrier QPSK for GNSS
72 GF(Q) LDPC decoder design for FPGA implementation
73 A high speed and low power VLSI multiplier using redundant binary booth
74 FPGA implementation of booths and baugh wooley multiplier using verilog
75 RTL design and implementation of BPSK modulation at low bit rate
76 Architecture and implementation of a vector SIMD multiply accumulate
77 32 bit MAC unit design using vedic multiplier
78 Low transition LFSR for bist based application
79 Arbitory density pattern based reduction of testing time in scan bist
80 FIR Filter Implementation using Modified Distributed Arithmetic Architecture
81 A Novel multirate adaptive fir filtering algorithm and structure
82 Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation
83 Low Complexity Multiplier for GF (2m )Based on All-One Polynomials
84 Design and Implementation of VLSI Systolic Array Multiplier for DSP Applications
85 A low power single phase clock distribution using VLSI technology
86 Test patterns of multiple siv vectors theory and application in bist schemes
87 Achieving reduced area by multi bit flip flop design
88 Radix 8 booth encoded modulo multipliers with adaptive delay for high dynamic range residue number system
89 A new VLSI architecture of parallel multiplier accumulator based on radix 2 modified booth algorithm
90 A VLIW vector media compressor with cascaded SIMD ALUs
91 Optimized implementation of FFT processor for OFDM systems
92 Finite state machine based vending machine controller with auto billing features
93 The design of high performance barrel integer adder
94 Architectural level power optimization techniques for multipliers
95 Design of characterization of parallel pre fix adders using FPGA
96 Design and minimization of reversible circuits for a data acquisition and storage system
97 Arithmetic & logic unit (ALU) design using reversible control unit
98 A distinguish between reversible and conventional logic gates
99 Design & implementation of MAC unit using reversible logic
100 An efficient implementation of floating point multiplier
101 Reducing the computation time in (short bit width) two s complement multipliers
102 Fault tolerant variable block carry skip logic (VBCSL) using parity preserving reversible gates
103 Design of a nano metric reversible 4 bit binary counter with parallel load
104 A New Reversible Design of BCD Adder
105 Pipelined Radix 2k Feed forward FFT Architectures
106 Parallel AES Encryption Engines for Many Core Processor Arrays
107 Reverse Circle Cipher for Personal and Network Security
108 A Topology Based Model for Railway Train Control Systems
109 A Novel Transistor Level Realization of Ultra Low Power High Speed Adiabatic Vedic Multiplier
110 Low Power High Throughput and Low Area Adaptive FIR Filter Based on Distributed Arithmetic
111 A New VLSI Architecture of parallel multiplier accumulator based on radix 2 Modified Booth Algorithm
112 Implementation of low cost Bist circuit for Public Key Crypto cores
113 Initialization based Test Pattern generation for Asynchronous circuits
114 Design a low power Booth Multiplier in FPGA
115 Implementation of MAC Unit
116 Design of Uart Transmitter module and Uart Receiver module
117 Verilog code for 3*3 Matrix Multiplication
118 Uart module for Real Time Application
119 Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
120 Design of Locally Clocked Asynchronous Finite State Machines Using Synchronous CAD Tools
121 Implementation of Binary to Floating Point Converter using HDL
122 High Performance and Power Efficient 32 bit Carry Select Adder using Hybrid PTL CMOS Logic Style
123 Implementation and Comparison of Effective Area Efficient Architectures for CSLA
124 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
125 Design of High Speed Low Power Multiplier using Reversible logic a Vedic Mathematical Approach
126 Design of High Performance 64 bit MAC Unit
127 Enhanced Area Efficient Architecture for 128 bit Modified CSLA
128 VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
129 Optimized Reversible Vedic Multipliers for High Speed Low Power Operations
130 Efficient Approaches to Design a Reversible Floating Point Divider
131 Design a DSP Operations using Vedic Mathematics
132 Adaptive Low Power RTPG for BIST based Test Applications
133 Design and Simulation of UART Serial Communication Module Based on Verilog
134 A New Reversible Design of BCD Adder
135 High Speed VLSI Architecture for General Linear LFSR Structures
136 Data Encryption Algorithm for Secure Communication
137 Built in Self Test Technique for Diagnosis of Delay Faults in Cluster Based Field Programmable Gate Arrays
138 Synthesis and Implementation of UART Using Verilog Codes
139 Power comparison of CMOS And Adiabatic Full Adder Circuits
140 Comments on Low Energy CSMT Carry Generators and Binary Adders
141 FPGA Based Implementation of a Double Precision IEEE Floating Point Adder
142 Design of High Speed Low Power Multiplier using Reversible logic A Vedic Mathematical Approach
143 Novel High Speed Vedic Mathematics Multiplier using Compressors
144 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
145 4 BIT SFQ Multiplier
146 Carry Tree Adder
147 Cordic Processor for Complex DPLL
148 Custom Floating Point Unit Generation
149 Cyclic Redundancy Checker Generator
150 Design of Data Encryption Standard (DES) for Data Encryption
151 Design And Synthesis Of Programmable Logic Block
152 Design Of Reversible Finite Field Arithmetic
153 Design of 16 Point Radix 4 FFT Algorithm
154 Design Of 32 Bit RISC Processor
155 Design of Finite Impulse Response Filter
156 Design Of Radix 2 Butterfly processor to prevent Overflow in The Arithmetic
157 Designing Efficient Online Testable Reversible Adders
158 Fault Secure Encoder
159 Floating Point Multiplier
160 Floating Point Vector Coprocessor
161 General Linear Feedback Shift Register
162 High Performance Complex Number Multiplier Using Booth Wallace Algorithm
163 High Accuracy Fixed Width Modified Booth Multipliers
164 Implementation of Hamming Code
165 LFSR Based Test Generator Synthesis
166 Low Power ALU Design By Ancient Mathematics
167 Parallel Prefix Adders Using FPGAS
168 Design Of Parallel Multiplier Based On RADIX 2 Modified Booth Algorithm
169 Reconfigurable Coprocessor for Redundant Radix 4 Arithmetic
170 Shift Register Based Data Transposition
171 Short Range MIMO Communications
172 Turbo Encoder For LTE Process
173 Universal Asynchronous Receiver Transmitter
174 Very Fast and Low Power Carry Select Adder Circuit
175 Area Delay Power Efficient Fixed Point LMS Adaptive Filter with Low Adaptation Delay
176 Low Power Area Efficient High Speed I O Circuit Techniques
177 Low Power High Throughput and Low Area Adaptive FIR Filter Based on Distributed Arithmetic
178 Smart Reliable Network on Chip
179 Time Based All Digital Technique for Analog Built in Self Test
180 A Low Power Single Phase Clock Distribution using VLSI technology
181 CORDIC based Fast Radix 2 DCT Algorithm
182 Design of Digit Serial FIR Filters Algorithms Architectures and a CAD Tool
183 Design of Low Energy High Performance Synchronous and Asynchronous 64 Point FFT
184 FFT Architectures for Real Valued Signals Based on Radix 2 by 3 & Radix 2 by 4 Algorithms
185 Pipelined Radix 2k Feed forward FFT Architectures
186 An Analytical Latency Model for Networks on Chip
187 Application Driven End to End Traffic Predictions for Low Power NoC Design
188 Low Latency Systolic Montgomery Multiplier for Finite Field GF(2^{m}) Based on Pentanomials
189 ffective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
190 High Throughput Compact Delay Insensitive Asynchronous NOC Router
191 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
192 Low Power Digital Signal Processing Using Approximate Adders
193 Comparison of Static and Dynamic Printed Organic Shift Registers
194 A High Performance D Flip Flop Design with Low Power Clocking System using MTCMOS
195 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
196 Performance Analysis of a New CMOS Output Buffer
197 Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
198 Asynchronous Design of Energy Efficient Full Adder
199 A Novel High Performance CMOS 1 Bit Full Adder Cell
200 Low Power and Area Efficient Carry Select Adder
201 Digital CMOS Parallel Counter Architecture Based on State Look Ahead Logic
202 Design Low Power 10T Full Adder Using Process and Circuit Techniques
203 A High Speed Low Power Multiplier Using an Advanced Spurious Power Suppression Technique
204 A Framework for Correction of Multi Bit Soft Errors
205 ASIC Design of Complex Multiplier
206 Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
207 Design and Implementation of Floating Point ALU
208 Design of Data Encryption Standard for Data Encryption
209 Synthesis and Implementation of UART Using Verillog Codes
210 Improved Architectures for a Fused Floating Point Add Subtract Unit
211 Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
212 Design and Implementation of Efficient Systolic Array Architecture
1 Low Power 10 Transistor Full Adder Design Based on Degenerate Pass Transistor
2 Design of 64 Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic
3 Design of low power high speed vlsi adder Subsystem
4 Synthesis and Implementation of UART using verilog Codes
5 HICPA A Hybrid Low Power Adder for High Performance Processors
6 Low Power and Area Efficient Carry Select Adder
7 Design and Implementation of Two Variable Multiplier Using KCM and Vedic
8 Design and Implementation of a High Performance Multiplier using HDL
9 Design of low power and high performance radix 4 multiplier
10 High Speed and Area Efficient Vedic Multiplier
11 Built In Generation of Functional Broadside Tests Using a Fixed Hardware
12 Low power variation aware flipflop
13 High speed Modified Booth Encoder multiplier for signed and unsigned
14 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
15 High Speed Signed Multiplier for Digital SignalProcessing Applications
16 Accumulator Based 3 Weight Pattern Generation
17 Design of Low Power TPG Using LP LFSR
18 A Real time Face Detection And Recognition System
19 Verilog Implementation of UART with Status Register
20 FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
21 Design and Implementation of Area optimized AES
22 A Low Power Single Phase Clock Multiband Flexible Divider
23 A Novel All Digital Multichannel Multimode RF Transmitter Using Delta Sigma Modulation
24 Pipelined Parallel FFT Architectures via Folding Transformation
25 An Efficient Architecture for 2D Lifting based Discrete Wavelet Transform
26 Power Efficient Pipelined Reconfigurable Fixed Width Baugh Wooley Multipliers
27 32 bit RISC CPU Based on MIPS High Speed Hardware Implementation of 1D DCT IDCT
28 Efficient FPGA implementation of convolution
29 High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
30 Design and Implementation of a 64 bit RISC Processor using Verilog HDL
31 Design and Implementation of Wi Fi MAC Transmit Protocol using VHDL
32 High speed parallel architecture for cyclic convolution based on FNT
33 Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
34 A Memory efficient Huffman Decoding Algorithm
35 Minimization of Switching Activities of Partial Products for Designing Low Power Multipliers
36 A New High Speed Architecture for Reed Solomon Decoder
37 The study of soc architecture design based on 32 bit embedded risc processor
38 An efficient fpga implementation of the advanced encryption standard algorithm
39 High speed modified booth encoder multiplier for signed and unsigned numbers
40 A new approach for high performance andefficient design of cordic processor
41 Fpga implementation of binary coded decimal Digit adders and multipliers
42 A high throughput configurable fft processor for wlan and wimax protocols
43 Design & implementation of floating point alu on a fpga processor
44 Design and implementation of low power fft ifft Processor for wireless communication
45 A novel approach for parallel CRC generation for high speed applications
46 An On Chip Delay Measurement Technique Using Signature Registers For Small Delay Defect Detection
47 Single Cycle Access Structure For Logic Test
48 A Low Power Single Phase Clock Multiband Flexible Divider ON MODULO 2n 1 ADDER DESIGN
49 Implementation of a Flexible and Synthesizable FFT Processor
50 A Multi Agent Framework for Thermal Aware Task Migration in Many Core Systems
51 A High Precision On Chip Path Delay Measurement Architecture
52 Full Fault Resilience and Relaxed Synchronization Requirements at the Cache Memory Interface
53 Location Cache Design and Performance Analysis for Chip Multiprocessors
54 Cusnoc Fast Full Chip Custom noc Generation
55 An Analytical Latency Model for Networks on Chip
56 Combined Architecture Algorithm Approach to Fast FPGA Routing
57 Addressing Transient and Permanent Faults in noc With Efficient Fault Tolerant Deflection Router
58 Semi Serial On Chip Link Implementation for Energy Efficiency and High Throughput
59 Dual Layer Adaptive Error Control for Network on Chip Links
60 A Variation Tolerant Current Mode Signaling Scheme for On Chip Interconnects
61 Reconfigurable Routers for Low Power and High Performance
62 Throughput Resource Efficient Reconfigurable Processor for Multimedia Applications
63 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
64 All Digital Wide Range Precharge Logic % Duty Cycle Corrector
65 A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
66 Low Power Pulse Triggered Flip Flop Design With Conditional Pulse Enhancement Scheme
67 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
68 Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
69 Efficient Majority Logic Fault Detection With Difference Set Codes for Memory Applications
70 Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications
71 Unified Architecture for Reed Solomon Decoder Combined With Burst Error Correction
72 Precision Aware Self Quantizing Hardware Architectures for the Discrete Wavelet Transform
73 Jointly Designed Architecture Aware LDPC Convolutional Codes and Memory Based Shuffled Decoder Architecture
74 Area Time Efficient Scaling Free CORDIC Using Generalized Micro Rotation Selection
75 CORDIC Designs for Fixed Angle of Rotation
76 Low Cost Self Test Techniques for Small rams in socs Using Enhanced IEEE 1500 Test Wrappers
77 Soft Error Resilient fpgas Using Built In D Hamming Product Code
78 Built In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
79 A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
80 An Area Effective Parity Based Fault Detection Technique for fpgas
81 Robust Secure Scan Design Against Scan Based Differential Cryptanalysis
82 A Pipeline VLSI Architecture for Fast Computation of the 2D Discrete Wavelet Transform
83 A Novel Filter Bank Multicarrier Scheme to Mitigate the Intrinsic Interference Application to MIMO Systems
84 A Wideband Digital RF Receiver Front End Employing a New Discrete Time Filter for m WiMAX
85 Cooperative Beam forming for Cognitive Radio Networks A Cross Layer Design
86 Good Synchronization Sequences for Permutation Codes
87 High Throughput Soft Output MIMO Detector Based on Path Preserving Trellis Search Algorithm
88 Low Complexity Iterative Channel Estimation for Turbo Receivers
89 Novel Interpolation and Polynomial Selection for Low Complexity Chase Soft Decision Reed Solomon Decoding
90 Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications
91 The Design of Hybrid Asymmetric FIR Analog Pulse Shaping Filters Against Receiver Timing Jitter
92 Transmission of 4 ASK Optical Fast OFDM With Chromatic Dispersion Compensation
93 State Space Frequency Domain Adaptive Filtering for Nonlinear Acoustic Echo Cancellation
94 Telephone Channel Compensation in Speaker Verification Using a Polynomial Approximation in the Log Filter Bank Energy Domain
95 A Fast Cryptography Pipelined Hardware developed in FPGA with Verilog HDL
96 A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits
97 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
98 A Low Power Low Cost Design of Primary Synchronization Signal Detection
99 A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS LMS Adaptive Filter
100 Area Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
101 Area Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
102 Design and Simulation of 32 Point FFT Using Radix 2 Algorithm for FPGA Implementation
103 Design of Digit Serial FIR Filters Algorithms Architectures and a CAD Tool
104 Pipelined Parallel FFT Architectures via Folding Transformation
105 Platform Independent Customizable UART Soft Core
106 Design and Implementation of a New Multilevel Inverter Topology
107 Digital Filters for Fast Harmonic Sequence Component Separation 3Ph
108 A Filter Bank and a Self Tuning Adaptive Filter for the Harmonic and Inter harmonic Estimation in Power Signals
109 Design of Low Voltage Low Power Operational Amplifier
110 Low Power Pulse Triggered Flip-Flop Design With Conditional Pulse Enhancement Scheme
111 Low Swing Differential Conditional Capturing Flip Flop for LC Resonant Clock Distribution Networks
112 Design & implementation of floating point ALU on a FPGA processor
113 Finite State Machine Motion Controller Servo Drives
114 Design and implementation of fault tolerant soft processors on FPGAs
115 MPSoC design approach of FPGA based controller for induction motor drive
116 VHDL Implementation of UART with Status Register
117 Power quality measurement system using FPGAs
118 Study of navigation methods based on embedded dual encoder
119 FPGA system on chip solution for a field oriented hybrid stepper motor control
120 FPGA Implementation of 8 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL
121 Optimization of Microcode Built In Self Test By Enhanced Faults Coverage for Embedded Memory
122 Low Power and Area Efficient Carry Select Adder
123 A High Performance D Flip Flop Design with Low Power Clocking System using MTCMOS Technique
124 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
125 The LUT SR family of uniform random Number generators for FPGA architectures
126 Extending the effective throughput of NOCS with Distributed shared buffer routers
127 Algorithm and the Optimal Finite Wordlength FIR Design
128 Channels with Single User Decoding
129 VLSI Implementation of Scalable Encryption Algorithm for Different Text and Processor Size
130 Designing of Low Power VLSI Circuits using Non Clocked Logic Style
131 Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility Speed and Complexity Trade Offs
132 The complexity of VLSI power delay optimization by interconnect resizing
133 Implementation of LFSR Counter Using CMOS VLSI Technology
134 Channel Height Estimation for VLSI Design
135 Efficient Mathematical Model on VLSI Circuit Partitioning
136 Area Efficient and Low Power VLSI Architecture of Min Sum LDPC Codes using Wave Pipelining
137 High Performance VLSI Architecture for FIR Filter using on the Fly Conversion Multiplier
138 VLSI Micro Architectures for High Radix Crossbars
139 A New Vlsi Architecture Of Parallel Multiplier Based On Radix 4 Modified Booth Algorithm Using Vhdl
140 Analysis of high performance vlsi for telecommunication data
141 Efficient Majority Logic Fault Detection With Difference Set Codes for Memory Applications
142 FFT Implementation with Fused Floating Point Operations
143 High Speed Architectures for Multiplication Using Reordered Normal Basis
144 Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
145 A High Accuracy Adaptive Conditional Probability Estimator for Fixed Width Booth Multipliers
146 Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
147 Area Time Efficient Scaling Free CORDIC Using Generalized Micro Rotation Selection
148 Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
149 Design and Simulation of 32 Point FFT Using Radix 2 Algorithm for FPGA Implementation
150 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
151 Design of Modified Low Power Booth Multiplier
152 Design of 64 bit low power parallel prefix vlsi adder for high speed Arithmetic circuits
153 Implementation of convolution encoder and viterbi decoder using verilog Hdl
154 FPGA Hardware of the LSB Steganography Method
155 BIST using genetic algorithm for error detection and correction
156 Optimizing Floating Point Units in Hybrid FPGAs
157 Bayesian Equalization for LDPC Channel Decoding
158 Low Complexity Soft Decoding of Huffman Codes and Iterative Joint Source Channel Decoding
159 Human Gait Modeling Using a Genetic Fuzzy Finite State Machine
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