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Engineering students have interest on Best Vlsi based Hspice projects ideas.In education level Hspice projects using Vlsi are very popular, we provide final year Hspice projects for engineering students.It will help to get real time knowledge

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TANNER PROJECTS | ||

1 | 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression | |

2 | A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA | |

3 | CMCS: Current-Mode Clock Synthesis | |

4 | Binary Adder Circuit Design Using Emerging MIGFET Devices | |

5 | A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier | |

6 | A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications | |

7 | Delay Analysis for Current Mode Threshold Logic Gate Designs | |

8 | A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar | |

9 | A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies | |

10 | A Memristor Based Binary Multiplier | |

11 | Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications | |

12 | Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays | |

13 | Design and Low Power Magnitude Comparator | |

14 | Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders | |

15 | Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology | |

16 | High Performance Ternary Adder using CNTFET | |

17 | High-performance engineered gate transistor-based compact digital circuits | |

18 | Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops | |

19 | Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits | |

20 | Optimized Memristor-Based Multipliers | |

21 | Probability-Driven Multibit Flip-Flop Integration With Clock Gating | |

22 | Register – Less NULL Conventional Logic | |

23 | Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template | |

24 | Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design | |

25 | Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design | |

26 | 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | |

27 | Fault Tolerant Logic Cell FPGA |

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BACK-END PROJECTS | ||

1 | A Low-Power Robust Easily Cascaded Penta MTJ-Based Combinational and Sequential Circuits | |

2 | Graph-Based Transistor Network GenerationMethod for Super gate Design | |

3 | A Comparator-Based Rail Clamp | |

4 | A Low Power Trainable Neuromorphic IntegratedCircuit That Is Tolerant to Device Mismatch | |

5 | Analysis of 8 bit RCA adder at different nanometer regime | |

6 | PNS-FCR: Flexible Charge RecyclingDynamic Circuit Technique forLow-Power Microprocessors | |

7 | Design Methodology for Voltage-Scaled Clock Distribution Networks | |

8 | One-Cycle Correction of Timing Errors in PipelinesWith Standard Clocked Elements | |

9 | A Single-Ended With Dynamic Feedback Control 8T Sub threshold SRAM Cell | |

10 | Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technologyfor Low-Voltage Operation | |

11 | A Low-Power Incremental Delta–SigmaADC for CMOS Image Sensors | |

12 | Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design | |

13 | A 55-GHz-Bandwidth Track-and-Hold Amplifierin 28-nm Low-Power CMOS | |

14 | Low-Power ASK Detector for Low ModulationIndexes and Rail-to-Rail Input Range | |

15 | Low-Power Variation-Tolerant Nonvolatile Lookup Table Design |

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BACK-END PROJECTS | ||

1 | Voltage mode implementation of highly accurate analog multiplier circuit | |

2 | Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme | |

3 | Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing | |

4 | Digtial to time converter using SET | |

5 | Design of high speed ternary full adder and threeinput XOR circuits using CNTFETs | |

6 | Design Method of Single-Flux-Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates | |

7 | Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata | |

8 | Design and Performance Evaluation of A Low Transistor Ternary CNTFET SRAM Cell | |

9 | A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process | |

10 | A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist | |

11 | A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology | |

12 | A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links | |

13 | A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique | |

14 | An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells | |

15 | Read Performance The Newest Barrier in Scaled STT-RAM | |

16 | On the Nonvolatile Performance of Flip-FlopSRAM Cells With a Single MTJ | |

17 | High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors | |

18 | High-Frequency CMOS Active Inductor Design Methodology and Noise Analysis | |

19 | Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model | |

20 | A CMOS PWM Transceiver Using Self-Referenced Edge Detection |