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Vlsi Backend Projects For Mtech Students

Mtech Final year Vlsi Backend Projects for students.Get the list of Vlsi Backend Projects For Mtech Students.We will give guidelines about the projects,so students will get the real time knowledge and how to do the projects in a correct manner

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1 Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique
2 Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
3 Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
4 Effect of Switched-Capacitor CMFB on the Gain of Fully Differential OpAmp for Design of Integrators
5 Passive Noise Shaping in SAR ADC With Improved Efficiency
6 A Low-Power Forward and Reverse Body Bias Generator in CMOS
7 Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique
8 Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder
9 Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
10 Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation
11 A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
12 A Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators
13 A Highly Efficient Composite Class-AB–AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads
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1 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression
2 A Compact memristor-CMOS hybrid Look-up-table Design and Potential Application in FPGA
3 CMCS: Current-Mode Clock Synthesis
4 Binary Adder Circuit Design Using Emerging MIGFET Devices
5 A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier
6 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
7 Delay Analysis for Current Mode Threshold Logic Gate Designs
8 A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar
9 A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies
10 A Memristor Based Binary Multiplier
11 Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
12 Bias-Induced Healing of Vmin Failures in Advanced SRAM Arrays
13 Design and Low Power Magnitude Comparator
14 Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
15 Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
16 High Performance Ternary Adder using CNTFET
17 High-performance engineered gate transistor-based compact digital circuits
18 Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
19 Exploiting Transistor-Level Reconfiguration to Optimize Combinational circuits
20 Optimized Memristor-Based Multipliers
21 Probability-Driven Multibit Flip-Flop Integration With Clock Gating
22 Register – Less NULL Conventional Logic
23 Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template
24 Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
25 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
26 Fault Tolerant Logic Cell FPGA
27 A band-selective low-noise amplifier using an improved tunable active inductor for 3–5 GHz UWB receivers
28 A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
29 A Low Power, Low Noise Amplifier For Recording Neural Signals
30 A Single-ended with Dynamic Feedback Control 8T Sub threshold SRAM Cell
31 Analysis and Design of the Classical CMOS Schmitt Trigger in Sub threshold Operation
32 Design And Analysis Of Combinational Coding Circuits Using Adiabatic Logic
33 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
34 Evolutionary Approach to Approximate Digital Circuits Design
35 Low Power 8-bit ALU Design Using Full Adder and Multiplexer
36 Powering Wearable Sensors with a Low-Power CMOS Piezoelectric Energy Harvesting Circuit
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