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Vlsi Arithmetic Core Projects For Mtech Students

Final Year Vlsi Arithmetic Core Projects.Get the List of Vlsi Arithmetic Core Projects.We will give guidelines about the projects,so students will get the real time knowledge and how to do the projects in a correct manner

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1 Approximate Quaternary Addition with the Fast Carry Chains of FPGAs
2 A Low-Power Configurable Adder for Approximate Applications
3 A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
4 A Low-Power Yet High-Speed Configurable Adder for Approximate Computing
5 A Simple Yet Efficient Accuracy- Configurable Adder Design
6 Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design
7 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers
8 A Cost-Effective Self-Healing Approach for Reliable Hardware Systems
9 Approximate Sum-of-Products Designs Based on Distributed Arithmetic
10 Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
11 Design, Evaluation and Application of Approximate High-Radix Dividers
12 Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors
13 Enhancing Fundamental Energy Limits of Field-Coupled Nano computing Circuits
14 Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors
15 Inexact Arithmetic Circuits for Energy Efficient loT Sensors Data Processing
16 Low-Power Addition with Borrow-Save Adders under Threshold Voltage Variability
17 Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary Signed Digit number system
18 On the Difficulty of Inserting Trojans in Reversible Computing Architectures
19 Optimizing Power-Accuracy trade-off in Approximate Adders
20 Power Efficient Approximate Booth Multiplier
21 Reducing the Hardware Complexity of a Parallel Prefix Adder
22 Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
23 Towards Efficient Modular Adders based on Reversible Circuits
24 A 32-bit 4×4 Bit-Slice RSFQ Matrix Multiplier
25 Research and implementation of hardware algorithms for multiplying binary numbers
26 Efficient Design for Fixed-Width Adder-Tree
27 Architecture Generator for Type-3 Unum Posit Adder/Subtractor
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1 A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation
2 A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers
3 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
4 Design of Power and Area Efficient Approximate Multipliers
5 Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
6 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
7 Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
8 A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n − 1, 2n + 1, 22n + 1, 22n+p}
9 Fast Energy Efficient Radix-16 Sequential Multiplier
10 DSP48E Efficient Floating Point Multiplier Architectures on FPGA
11 Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems
12 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic
13 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
14 Design and Analysis of Multiplier Using Approximate 15-4 Compressor
15 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
16 High Performance Parallel Decimal Multipliers using Hybrid BCD Codes
17 High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder
18 Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
19 Multi-operand logarithmic addition/subtraction based on Fractional Normalization
20 On the Implementation of Computation-in-Memory Parallel Adder
21 Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor
22 Probabilistic Error Analysis of Approximate Recursive Multipliers
23 RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder
24 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
25 Comparative study of 16-order FIR filter design using different multiplication techniques
26 Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm
27 An Optimised 3x3 Shift and Add Multiplier on FPGA
28 Optimization of Constant Matrix Multiplication with Low Power and High Throughput
29 Realization of a hardware generator for the Sum of Absolute Difference component
30 A Structured Visual approach to GALS Modelling and Verification of Communication Circuits
31 Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials
32 A Novel Data Format for Approximate Arithmetic Computing
33 Automatic Generation of Farmally Prover temper resistant Galioes field multiplier based on generalized masking scheme
34 Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
35 High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
36 DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
37 Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition
38 Reconfigurable Constant Multiplication for FPGAs
39 Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
40 Area-time Efficient Architecture of FFT-based Montgomery Multiplication
41 Efficient RNS Scalers for the Extended Three-Moduli Set(2n -1; 2n+p; 2n + 1)
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1 A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System
2 An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA
3 An Improved Signed Digit Representation Approach for Constant Vector Multiplication
4 Area-Delay Efficient Digit-Serial Multiplier Based on kPartitioning Scheme Combined With TMVP Block Recombination Approach
5 Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design
6 Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs
7 Logic Synthesis in Reversible PLA
8 MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding
9 Multi Precision Arithmetic Adders
10 Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit
11 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
12 Low complexity and area efficient reconfigurable multimode inter leaver address generator for multi standard radios
13 Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2m)
14 Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest
15 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
16 A Modified Partial Product Generator for Redundant Binary Multipliers
17 Arithmetic algorithms for extended precisionusing floating-point expansions
18 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
19 Performance/Power Space Exploration for Binary64 Division Units
20 On Efficient Retiming of Fixed-Point Circuits
21 Hybrid LUT/Multiplexer FPGA Logic Architectures
22 VLSI Design for Convolutive BlindSource Separation
23 Concept, Design, and Implementation of Reconfigurable CORDIC
24 Ultralow-Energy Variation-Aware Design: Adder Architecture Study
25 Floating-Point Butterfly Architecture Based on Binary SignedDigit Representation
26 Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier
27 Design and Analysis of Inexact Floating-Point Adders
28 Low-Cost High-Performance VLSI Architecture forMontgomery Modular Multiplication
29 High speed hybrid double multiplication architectures using new serial out bit level mastrovito multiplier
30 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
31 Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolution Codes
32 A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND-Flash Memory
33 Implementing Minimum-Energy-Point Systems With Adaptive Logic
34 High-Performance NB-LDPC Decoder With Reduction of Message Exchange
35 Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device
36 Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors
37 Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application
38 Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range
39 Understanding the Relation Between the Performance and Reliability of NAND Flash/SCM Hybrid Solid-State Drive
40 Optimized Built-In Self-Repair for Multiple Memories
41 A High-Throughput Hardware Design of a One-Dimensional SPIHT Algorithm
42 Network-on-Chip for Turbo Decoders
43 Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
44 Speculative Look ahead for Energy-Efficient Microprocessors
45 Efficient Synchronization for Distributed Embedded Multiprocessors
46 NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices
47 A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies
48 Knowledge-Based Neural Network Model for FPGA Logical Architecture Development
49 A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes
50 A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing
51 Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems
52 Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division
53 Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching
54 Trigger-Centric Loop Mapping on CGRAs
55 Area-Aware Cache Update Trackers for Post silicon Validation
56 PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash
57 Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
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1 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
2 A Modified Partial Product Generator for Redundant Binary Multipliers
3 Design & Analysis of 16 bit RISC Processor Using low Power Pipelining
4 Design and Analysis of Approximate Compressors for Multiplication
5 Design and Implementation of 16 x 16 Multiplier Using Vedic Mathematics
6 Design and implementation of fast floating point multiplier unit
7 Area and frequency optimized 1024 point Radix-2 FFT processor on FPGA
8 Design and Simulation of Single Layered Logic Generator Block using Quantum Dot Cellular Automata
9 Design of area and power aware reduced Complexity Wallace Tree multiplier
10 Design of area and power efficient digital FIR filter using modified MAC unit
11 Design of low power and high speed Carry Select Adder using Brent Kung adder
12 Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
13 FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers
14 FPGA implementation of vedic floating point multiplier
15 FPGA realization and performance evaluation of fixed-width modified Baugh-Wooley multiplier
16 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
17 FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration
18 Intelligent and Adaptive Traffic Light Controller using FPGA
19 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
20 Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
21 A High-Speed FPGA Implementation of an RSD-Based ECC Processor
22 Analysis of ternary multiplier using booth encoding technique
23 A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM
24 HMFPCC - Hybrid-mode floating point conversion co-processor
25 On the Analysis of Reversible Booth's Multiplier
26 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
27 Reverse Converter Design via Parallel-Prefix Adders Novel Components, Methodology, and Implementations
28 Coming SoonRevisiting Central Limit Theorem Accurate Gaussian Random Number Generation in VLSI
29 Advanced low power RISC processor design using MIPS instruction set
30 RTL implementation for AMBA ASB APB protocol at system on chip level
31 Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
32 Technology optimized fixed-point bit-parallel multiplier for LUT based FPGAs
33 Truncated ternary multipliers
34 An_efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
1 Area Delay Power Efficient Carry Select Adder
2 On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
3 Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
4 A Method to Extend Orthogonal Latin Square Codes
5 Design and Estimation of delay power and area for Parallel prefix adders
6 Design and FPGA implementation of compressor based Vedic multiplier
7 A Combined SDC SDF Architecture for Normal I/O Pipelined Radix-2 FFT
8 Area Delay Efficient Binary Adders in QCA
9 Test Versus Security Past and Present
10 Skewed Load Test Cubes Based on Functional Broadside Tests for a Low Power Test Set
11 High Speed Convolution and De convolution Algorithm
12 Fast Radix 10 Multiplication Using Redundant BCD Codes
13 Low Complexity Low Latency Architecture for Matching of Data Encoded With Hard Systematic Error Correcting Codes
14 Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing
15 Design of High Performance 64 bit MAC Unit
16 Thwarting Scan Based Attacks on Secure-ICs With On-Chip Comparison
17 Low Power Test Generation by Merging of Functional Broadside Test Cubes
18 Design of Dedicated Reversible Quantum Circuitry for Square Computation
19 A Look Ahead Clock Gating Based on Auto Gated Flip Flops
20 A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)
21 Aging Aware Reliable Multiplier Design With Adaptive Hold Logic
22 An Accuracy Adjustment Fixed Width Booth Multiplier Based on Multilevel Conditional Probability
23 Arithmetic Based Binary to RNS Converter Modulo {2n ± k} for jn-Bit Dynamic Range
24 Critical Path Analysis and Low Complexity Implementation of the LMS Adaptive Algorithm
25 Design Flow for Flip Flop Grouping in Data Driven Clock Gating
26 Design of Efficient Binary Comparators in Quantum Dot Cellular Automata
27 Efficient Hardware Implementation of Encoder and Decoder for Golay Code
28 Efficient Integer DCT Architectures for HEVC
29 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}
30 Fault Tolerant Parallel Filters Based on Error Correction Codes
31 Low Voltage and Low Power 64-bit Hybrid Adder Design Based on Radix-4 Prefix Tree Structure
32 On the Design of Efficient Modulo 2n+1 Multiply Add Add Units
33 Reverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations
34 FPGA based partial reconfigurable fir filter design
35 An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation Filter for Multistandard DUC
36 An Efficient Field Programmable Gate ArrayImplementation of Double Precision Floating Point Multiplier using VHDL
37 An Overview of Advance Microcontroller Bus Architecture Relate on AHB Bridge
38 FPGA-Based Bit Error Rate PerformanceMeasurement of Wireless Systems
1 Thwarting Scan Based Attacks on Secure ICs With On Chip Comparison
2 Design for testablity support for launch and capture power reduction in launch of shift and launch of capture testing
3 Area Delay Efficient Binary Adders in QCA
4 CMOS Charge Pump With No Reversion Loss and Enhanced Drivability
5 Efficent Register renaming and recovery for high performance Processors
6 Low Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple
7 Enhanced memory reliabilty against multiple cells upsets using decimal
8 Average 8T Differential Sensing Subthreshold SRAM With Bit Interleaving
9 Reliable Concurrent Error Detection Architectures for Extended Euclidean
10 CORDIC Designs for Fixed Angle of Rotation
11 A Built In Repair Analyzer With Optimal Repair Rate for Word Oriented
12 Built In Generation of Functional Broadside Tests Using a Fixed Hardware
13 A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless
14 Design and Implementation of an On Chip Permutation Network for Multiprocessor
15 Glitch Free NAND Based Digitally Controlled Delay Lines
16 Computing Two Pattern Test Cubes for Transition Path Delay Faults
17 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density
18 A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture
19 Achieving High Performance On Chip Networks With Shared Buffer Routers
20 Analysis and Design of a Low Voltage Low Power Double Tail Comparator
21 Area Delay Power Efficient Fixed Point LMS Adaptive Filter With Low Adaptation
22 Comparative Study of Various Latch Type Sense Amplifiers
23 Delay Test for Diagnosis of Power Switches
24 Design of a Low Voltage Low Dropout Regulator
25 High resolution all digital duty cycle corrector in65nm cmos technology
26 Incremental Trace Buffer Insertion for FPGA Debug
27 Low Power Digital Signal Processor Architecture for Wireless Sensor Nodes
28 Memory Footprint Reduction for Power Efficient Realization of 2D Finite
29 On Chip Memory Hierarchy in One coarse grained reconfigurable architecture
30 On the Field Test and Configuration Infrastructure for 2D Mesh NoCs
31 Software Hardware Parallel Long Period Random Number Generation
32 Parasitics Aware Design of Symmetric and Asymmetric Gate Work function
33 Power Efficient Class AB Op Amps With High and symmetric slew rate
34 A Novel Modulo Adder for Residue Number System
35 Restoration Based Procedures With Set Covering Heuristics for Static Test
36 Smart Reliable Network on Chip
37 Test Compaction by Sharing of Transparent Scan Sequences Among Logic blocks
38 Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
39 Variation Aware Variable Latency Design
40 An Efficient Interpolation Based Chase BCH decoder
41 Energy efficient code converters by using reversible logic gates
42 An efficient SQRT architecture of Carry Select adder design by Boolean
43 An efficient high speed Wallace tree multiplier
44 Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA
45 Design of High Efficiency Carry Select Adder Using SQRT Technique
46 FPGA based implementation of a double precision IEEE floating point adder
47 LFSR reseeding scheme for achieving test coverage
48 Optimized architecture for Floating Point computation Unit
49 Radix 4 and Radix 8 Booth Encoded Multi Modulus Multipliers
50 Sharing Logic for Built In Generation of Functional Broadside
51 Implementation of cryptographic algorithm on FPGA
52 128 bit carry select adder having less area and delay
53 FPGA implementation high speed vedic multiplier using barrel shifter
54 Improved Design of Low Power TPG Using LPLFSR
55 HICPA 64 bit hybrid low power adder for high performance processors
56 128 bit low power VLSI adder subsystem
57 Parity preserving logic based fault tolerant reversible ALU
58 Efficient concurrent BIST with comparator based response analayzer
59 Area efficient high speed low power multiplier architecture for multirate filter design
60 Used self controllable voltage level techniques to reduce leakage currents
61 Minimization leakage current of full adder using deep sub micron CMOS
62 Normaliation of floating point multiplication using verilog hdl
63 Design and implementation of truncated multipliers for precision improvement
64 Design of high speed hardware efficient 4 bit sfq multiplier
65 VHdl implementation of non restoring division algorithem using high speed
66 Implementation of fixed point square root algorithem on fpga hardware
67 Platform independent customizable UART soft core
68 Design and Implementation of FPGA based High Resolution Digital Pulse
69 Design and implementation of floating point ALU in FPGA
70 Hardware implementation of truncated multiplier based on multiplier
71 Time multiplexed offset carrier QPSK for GNSS
72 GF(Q) LDPC decoder design for FPGA implementation
73 A high speed and low power VLSI multiplier using redundant binary booth
74 FPGA implementation of booths and baugh wooley multiplier using verilog
75 RTL design and implementation of BPSK modulation at low bit rate
76 Architecture and implementation of a vector SIMD multiply accumulate
77 32 bit MAC unit design using vedic multiplier
78 Low transition LFSR for bist based application
79 Arbitory density pattern based reduction of testing time in scan bist
80 FIR Filter Implementation using Modified Distributed Arithmetic Architecture
81 A Novel multirate adaptive fir filtering algorithm and structure
82 Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation
83 Low Complexity Multiplier for GF (2m )Based on All-One Polynomials
84 Design and Implementation of VLSI Systolic Array Multiplier for DSP Applications
85 A low power single phase clock distribution using VLSI technology
86 Test patterns of multiple siv vectors theory and application in bist schemes
87 Achieving reduced area by multi bit flip flop design
88 Radix 8 booth encoded modulo multipliers with adaptive delay for high dynamic range residue number system
89 A new VLSI architecture of parallel multiplier accumulator based on radix 2 modified booth algorithm
90 A VLIW vector media compressor with cascaded SIMD ALUs
91 Optimized implementation of FFT processor for OFDM systems
92 Finite state machine based vending machine controller with auto billing features
93 The design of high performance barrel integer adder
94 Architectural level power optimization techniques for multipliers
95 Design of characterization of parallel pre fix adders using FPGA
96 Design and minimization of reversible circuits for a data acquisition and storage system
97 Arithmetic & logic unit (ALU) design using reversible control unit
98 A distinguish between reversible and conventional logic gates
99 Design & implementation of MAC unit using reversible logic
100 An efficient implementation of floating point multiplier
101 Reducing the computation time in (short bit width) two s complement multipliers
102 Fault tolerant variable block carry skip logic (VBCSL) using parity preserving reversible gates
103 Design of a nano metric reversible 4 bit binary counter with parallel load
104 A New Reversible Design of BCD Adder
105 Pipelined Radix 2k Feed forward FFT Architectures
106 Parallel AES Encryption Engines for Many Core Processor Arrays
107 Reverse Circle Cipher for Personal and Network Security
108 A Topology Based Model for Railway Train Control Systems
109 A Novel Transistor Level Realization of Ultra Low Power High Speed Adiabatic Vedic Multiplier
110 Low Power High Throughput and Low Area Adaptive FIR Filter Based on Distributed Arithmetic
111 A New VLSI Architecture of parallel multiplier accumulator based on radix 2 Modified Booth Algorithm
112 Implementation of low cost Bist circuit for Public Key Crypto cores
113 Initialization based Test Pattern generation for Asynchronous circuits
114 Design a low power Booth Multiplier in FPGA
115 Implementation of MAC Unit
116 Design of Uart Transmitter module and Uart Receiver module
117 Verilog code for 3*3 Matrix Multiplication
118 Uart module for Real Time Application
119 Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
120 Design of Locally Clocked Asynchronous Finite State Machines Using Synchronous CAD Tools
121 Implementation of Binary to Floating Point Converter using HDL
122 High Performance and Power Efficient 32 bit Carry Select Adder using Hybrid PTL CMOS Logic Style
123 Implementation and Comparison of Effective Area Efficient Architectures for CSLA
124 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
125 Design of High Speed Low Power Multiplier using Reversible logic a Vedic Mathematical Approach
126 Design of High Performance 64 bit MAC Unit
127 Enhanced Area Efficient Architecture for 128 bit Modified CSLA
128 VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
129 Optimized Reversible Vedic Multipliers for High Speed Low Power Operations
130 Efficient Approaches to Design a Reversible Floating Point Divider
131 Design a DSP Operations using Vedic Mathematics
132 Adaptive Low Power RTPG for BIST based Test Applications
133 Design and Simulation of UART Serial Communication Module Based on Verilog
134 A New Reversible Design of BCD Adder
135 High Speed VLSI Architecture for General Linear LFSR Structures
136 Data Encryption Algorithm for Secure Communication
137 Built in Self Test Technique for Diagnosis of Delay Faults in Cluster Based Field Programmable Gate Arrays
138 Synthesis and Implementation of UART Using Verilog Codes
139 Power comparison of CMOS And Adiabatic Full Adder Circuits
140 Comments on Low Energy CSMT Carry Generators and Binary Adders
141 FPGA Based Implementation of a Double Precision IEEE Floating Point Adder
142 Design of High Speed Low Power Multiplier using Reversible logic A Vedic Mathematical Approach
143 Novel High Speed Vedic Mathematics Multiplier using Compressors
144 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
145 4 BIT SFQ Multiplier
146 Carry Tree Adder
147 Cordic Processor for Complex DPLL
148 Custom Floating Point Unit Generation
149 Cyclic Redundancy Checker Generator
150 Design of Data Encryption Standard (DES) for Data Encryption
151 Design And Synthesis Of Programmable Logic Block
152 Design Of Reversible Finite Field Arithmetic
153 Design of 16 Point Radix 4 FFT Algorithm
154 Design Of 32 Bit RISC Processor
155 Design of Finite Impulse Response Filter
156 Design Of Radix 2 Butterfly processor to prevent Overflow in The Arithmetic
157 Designing Efficient Online Testable Reversible Adders
158 Fault Secure Encoder
159 Floating Point Multiplier
160 Floating Point Vector Coprocessor
161 General Linear Feedback Shift Register
162 High Performance Complex Number Multiplier Using Booth Wallace Algorithm
163 High Accuracy Fixed Width Modified Booth Multipliers
164 Implementation of Hamming Code
165 LFSR Based Test Generator Synthesis
166 Low Power ALU Design By Ancient Mathematics
167 Parallel Prefix Adders Using FPGAS
168 Design Of Parallel Multiplier Based On RADIX 2 Modified Booth Algorithm
169 Reconfigurable Coprocessor for Redundant Radix 4 Arithmetic
170 Shift Register Based Data Transposition
171 Short Range MIMO Communications
172 Turbo Encoder For LTE Process
173 Universal Asynchronous Receiver Transmitter
174 Very Fast and Low Power Carry Select Adder Circuit
175 Area Delay Power Efficient Fixed Point LMS Adaptive Filter with Low Adaptation Delay
176 Low Power Area Efficient High Speed I O Circuit Techniques
177 Low Power High Throughput and Low Area Adaptive FIR Filter Based on Distributed Arithmetic
178 Smart Reliable Network on Chip
179 Time Based All Digital Technique for Analog Built in Self Test
180 A Low Power Single Phase Clock Distribution using VLSI technology
181 CORDIC based Fast Radix 2 DCT Algorithm
182 Design of Digit Serial FIR Filters Algorithms Architectures and a CAD Tool
183 Design of Low Energy High Performance Synchronous and Asynchronous 64 Point FFT
184 FFT Architectures for Real Valued Signals Based on Radix 2 by 3 & Radix 2 by 4 Algorithms
185 Pipelined Radix 2k Feed forward FFT Architectures
186 An Analytical Latency Model for Networks on Chip
187 Application Driven End to End Traffic Predictions for Low Power NoC Design
188 Low Latency Systolic Montgomery Multiplier for Finite Field GF(2^{m}) Based on Pentanomials
189 ffective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
190 High Throughput Compact Delay Insensitive Asynchronous NOC Router
191 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
192 Low Power Digital Signal Processing Using Approximate Adders
193 Comparison of Static and Dynamic Printed Organic Shift Registers
194 A High Performance D Flip Flop Design with Low Power Clocking System using MTCMOS
195 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
196 Performance Analysis of a New CMOS Output Buffer
197 Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
198 Asynchronous Design of Energy Efficient Full Adder
199 A Novel High Performance CMOS 1 Bit Full Adder Cell
200 Low Power and Area Efficient Carry Select Adder
201 Digital CMOS Parallel Counter Architecture Based on State Look Ahead Logic
202 Design Low Power 10T Full Adder Using Process and Circuit Techniques
203 A High Speed Low Power Multiplier Using an Advanced Spurious Power Suppression Technique
204 A Framework for Correction of Multi Bit Soft Errors
205 ASIC Design of Complex Multiplier
206 Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
207 Design and Implementation of Floating Point ALU
208 Design of Data Encryption Standard for Data Encryption
209 Synthesis and Implementation of UART Using Verillog Codes
210 Improved Architectures for a Fused Floating Point Add Subtract Unit
211 Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
212 Design and Implementation of Efficient Systolic Array Architecture
1 Low Power 10 Transistor Full Adder Design Based on Degenerate Pass Transistor
2 Design of 64 Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic
3 Design of low power high speed vlsi adder Subsystem
4 Synthesis and Implementation of UART using verilog Codes
5 HICPA A Hybrid Low Power Adder for High Performance Processors
6 Low Power and Area Efficient Carry Select Adder
7 Design and Implementation of Two Variable Multiplier Using KCM and Vedic
8 Design and Implementation of a High Performance Multiplier using HDL
9 Design of low power and high performance radix 4 multiplier
10 High Speed and Area Efficient Vedic Multiplier
11 Built In Generation of Functional Broadside Tests Using a Fixed Hardware
12 Low power variation aware flipflop
13 High speed Modified Booth Encoder multiplier for signed and unsigned
14 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
15 High Speed Signed Multiplier for Digital SignalProcessing Applications
16 Accumulator Based 3 Weight Pattern Generation
17 Design of Low Power TPG Using LP LFSR
18 A Real time Face Detection And Recognition System
19 Verilog Implementation of UART with Status Register
20 FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
21 Design and Implementation of Area optimized AES
22 A Low Power Single Phase Clock Multiband Flexible Divider
23 A Novel All Digital Multichannel Multimode RF Transmitter Using Delta Sigma Modulation
24 Pipelined Parallel FFT Architectures via Folding Transformation
25 An Efficient Architecture for 2D Lifting based Discrete Wavelet Transform
26 Power Efficient Pipelined Reconfigurable Fixed Width Baugh Wooley Multipliers
27 32 bit RISC CPU Based on MIPS High Speed Hardware Implementation of 1D DCT IDCT
28 Efficient FPGA implementation of convolution
29 High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
30 Design and Implementation of a 64 bit RISC Processor using Verilog HDL
31 Design and Implementation of Wi Fi MAC Transmit Protocol using VHDL
32 High speed parallel architecture for cyclic convolution based on FNT
33 Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
34 A Memory efficient Huffman Decoding Algorithm
35 Minimization of Switching Activities of Partial Products for Designing Low Power Multipliers
36 A New High Speed Architecture for Reed Solomon Decoder
37 The study of soc architecture design based on 32 bit embedded risc processor
38 An efficient fpga implementation of the advanced encryption standard algorithm
39 High speed modified booth encoder multiplier for signed and unsigned numbers
40 A new approach for high performance andefficient design of cordic processor
41 Fpga implementation of binary coded decimal Digit adders and multipliers
42 A high throughput configurable fft processor for wlan and wimax protocols
43 Design & implementation of floating point alu on a fpga processor
44 Design and implementation of low power fft ifft Processor for wireless communication
45 A novel approach for parallel CRC generation for high speed applications
46 An On Chip Delay Measurement Technique Using Signature Registers For Small Delay Defect Detection
47 Single Cycle Access Structure For Logic Test
48 A Low Power Single Phase Clock Multiband Flexible Divider ON MODULO 2n 1 ADDER DESIGN
49 Implementation of a Flexible and Synthesizable FFT Processor
50 A Multi Agent Framework for Thermal Aware Task Migration in Many Core Systems
51 A High Precision On Chip Path Delay Measurement Architecture
52 Full Fault Resilience and Relaxed Synchronization Requirements at the Cache Memory Interface
53 Location Cache Design and Performance Analysis for Chip Multiprocessors
54 Cusnoc Fast Full Chip Custom noc Generation
55 An Analytical Latency Model for Networks on Chip
56 Combined Architecture Algorithm Approach to Fast FPGA Routing
57 Addressing Transient and Permanent Faults in noc With Efficient Fault Tolerant Deflection Router
58 Semi Serial On Chip Link Implementation for Energy Efficiency and High Throughput
59 Dual Layer Adaptive Error Control for Network on Chip Links
60 A Variation Tolerant Current Mode Signaling Scheme for On Chip Interconnects
61 Reconfigurable Routers for Low Power and High Performance
62 Throughput Resource Efficient Reconfigurable Processor for Multimedia Applications
63 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
64 All Digital Wide Range Precharge Logic % Duty Cycle Corrector
65 A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
66 Low Power Pulse Triggered Flip Flop Design With Conditional Pulse Enhancement Scheme
67 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
68 Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
69 Efficient Majority Logic Fault Detection With Difference Set Codes for Memory Applications
70 Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications
71 Unified Architecture for Reed Solomon Decoder Combined With Burst Error Correction
72 Precision Aware Self Quantizing Hardware Architectures for the Discrete Wavelet Transform
73 Jointly Designed Architecture Aware LDPC Convolutional Codes and Memory Based Shuffled Decoder Architecture
74 Area Time Efficient Scaling Free CORDIC Using Generalized Micro Rotation Selection
75 CORDIC Designs for Fixed Angle of Rotation
76 Low Cost Self Test Techniques for Small rams in socs Using Enhanced IEEE 1500 Test Wrappers
77 Soft Error Resilient fpgas Using Built In D Hamming Product Code
78 Built In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
79 A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
80 An Area Effective Parity Based Fault Detection Technique for fpgas
81 Robust Secure Scan Design Against Scan Based Differential Cryptanalysis
82 A Pipeline VLSI Architecture for Fast Computation of the 2D Discrete Wavelet Transform
83 A Novel Filter Bank Multicarrier Scheme to Mitigate the Intrinsic Interference Application to MIMO Systems
84 A Wideband Digital RF Receiver Front End Employing a New Discrete Time Filter for m WiMAX
85 Cooperative Beam forming for Cognitive Radio Networks A Cross Layer Design
86 Good Synchronization Sequences for Permutation Codes
87 High Throughput Soft Output MIMO Detector Based on Path Preserving Trellis Search Algorithm
88 Low Complexity Iterative Channel Estimation for Turbo Receivers
89 Novel Interpolation and Polynomial Selection for Low Complexity Chase Soft Decision Reed Solomon Decoding
90 Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications
91 The Design of Hybrid Asymmetric FIR Analog Pulse Shaping Filters Against Receiver Timing Jitter
92 Transmission of 4 ASK Optical Fast OFDM With Chromatic Dispersion Compensation
93 State Space Frequency Domain Adaptive Filtering for Nonlinear Acoustic Echo Cancellation
94 Telephone Channel Compensation in Speaker Verification Using a Polynomial Approximation in the Log Filter Bank Energy Domain
95 A Fast Cryptography Pipelined Hardware developed in FPGA with Verilog HDL
96 A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits
97 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
98 A Low Power Low Cost Design of Primary Synchronization Signal Detection
99 A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS LMS Adaptive Filter
100 Area Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
101 Area Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
102 Design and Simulation of 32 Point FFT Using Radix 2 Algorithm for FPGA Implementation
103 Design of Digit Serial FIR Filters Algorithms Architectures and a CAD Tool
104 Pipelined Parallel FFT Architectures via Folding Transformation
105 Platform Independent Customizable UART Soft Core
106 Design and Implementation of a New Multilevel Inverter Topology
107 Digital Filters for Fast Harmonic Sequence Component Separation 3Ph
108 A Filter Bank and a Self Tuning Adaptive Filter for the Harmonic and Inter harmonic Estimation in Power Signals
109 Design of Low Voltage Low Power Operational Amplifier
110 Low Power Pulse Triggered Flip-Flop Design With Conditional Pulse Enhancement Scheme
111 Low Swing Differential Conditional Capturing Flip Flop for LC Resonant Clock Distribution Networks
112 Design & implementation of floating point ALU on a FPGA processor
113 Finite State Machine Motion Controller Servo Drives
114 Design and implementation of fault tolerant soft processors on FPGAs
115 MPSoC design approach of FPGA based controller for induction motor drive
116 VHDL Implementation of UART with Status Register
117 Power quality measurement system using FPGAs
118 Study of navigation methods based on embedded dual encoder
119 FPGA system on chip solution for a field oriented hybrid stepper motor control
120 FPGA Implementation of 8 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL
121 Optimization of Microcode Built In Self Test By Enhanced Faults Coverage for Embedded Memory
122 Low Power and Area Efficient Carry Select Adder
123 A High Performance D Flip Flop Design with Low Power Clocking System using MTCMOS Technique
124 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
125 The LUT SR family of uniform random Number generators for FPGA architectures
126 Extending the effective throughput of NOCS with Distributed shared buffer routers
127 Algorithm and the Optimal Finite Wordlength FIR Design
128 Channels with Single User Decoding
129 VLSI Implementation of Scalable Encryption Algorithm for Different Text and Processor Size
130 Designing of Low Power VLSI Circuits using Non Clocked Logic Style
131 Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility Speed and Complexity Trade Offs
132 The complexity of VLSI power delay optimization by interconnect resizing
133 Implementation of LFSR Counter Using CMOS VLSI Technology
134 Channel Height Estimation for VLSI Design
135 Efficient Mathematical Model on VLSI Circuit Partitioning
136 Area Efficient and Low Power VLSI Architecture of Min Sum LDPC Codes using Wave Pipelining
137 High Performance VLSI Architecture for FIR Filter using on the Fly Conversion Multiplier
138 VLSI Micro Architectures for High Radix Crossbars
139 A New Vlsi Architecture Of Parallel Multiplier Based On Radix 4 Modified Booth Algorithm Using Vhdl
140 Analysis of high performance vlsi for telecommunication data
141 Efficient Majority Logic Fault Detection With Difference Set Codes for Memory Applications
142 FFT Implementation with Fused Floating Point Operations
143 High Speed Architectures for Multiplication Using Reordered Normal Basis
144 Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
145 A High Accuracy Adaptive Conditional Probability Estimator for Fixed Width Booth Multipliers
146 Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
147 Area Time Efficient Scaling Free CORDIC Using Generalized Micro Rotation Selection
148 Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
149 Design and Simulation of 32 Point FFT Using Radix 2 Algorithm for FPGA Implementation
150 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
151 Design of Modified Low Power Booth Multiplier
152 Design of 64 bit low power parallel prefix vlsi adder for high speed Arithmetic circuits
153 Implementation of convolution encoder and viterbi decoder using verilog Hdl
154 FPGA Hardware of the LSB Steganography Method
155 BIST using genetic algorithm for error detection and correction
156 Optimizing Floating Point Units in Hybrid FPGAs
157 Bayesian Equalization for LDPC Channel Decoding
158 Low Complexity Soft Decoding of Huffman Codes and Iterative Joint Source Channel Decoding
159 Human Gait Modeling Using a Genetic Fuzzy Finite State Machine
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