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Vlsi Front End Projects For Btech Students

Btech Final year Vlsi Front End Projects for students.Get the list of Btech Vlsi Front End Projects.We will give guidelines about the projects,so students will get the real time knowledge and how to do the projects in a correct manner

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VLSI FRONTEND PROJECTS
1 Approximate Quaternary Addition with the Fast Carry Chains of FPGAs
2 A Low-Power Configurable Adder for Approximate Applications
3 A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
4 Optimizing Power-Accuracy trade-off in Approximate Adders
5 A Simple Yet Efficient Accuracy- Configurable Adder Design
6 A Low Power CMOS Temperature Sensor Frontend for RFID Tags
7 Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability
8 A Low-Power Yet High-Speed Configurable Adder for Approximate Computing
9 Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
10 Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
11 A Double Error Correction Code for 32-bit Data Words with Efficient Decoding
12 An Efficient VLSI Architecture for Convolution Based DWT Using MAC
13 High Speed Power Efficient Carry Select Adder Design
14 Design of Majority Logic (ML) Based Approximate Full Adders
15 High Performance VLSI Architecture for Transpose Form FIR Filter using Integrated Module
16 Fault-tolerant design and analysis of QCA based circuits
17 Unbiased Rounding for HUB Floating-point Addition
18 Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error
19 Combined Pseudo-Exhaustive and Deterministic Testing of Array Multipliers
20 Nonlinear Binary Codes and Their Utilization for Test
21 A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher
22 A Novel approach for design of Real Time Traffic Control System using Verilog HDL
23 An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA
24 An Inter-Layer Interconnect BIST Solution for Monolithic 3D ICs
25 Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications
26 Built-in Test for Hidden Delay Faults
27 Design and Verilog HDL Implementation of Carry Skip Adder Using Kogge-Stone Tree Logic
28 High Speed Efficient Multiplier Design using Reversible Gates
29 High-Performance NTT Architecture for Large Integer Multiplication
30 Inexact Arithmetic Circuits for Energy Efficient loT Sensors Data Processing
31 A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test
32 A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits
33 Automotive functional safety assurance by post with sequential observation
34 Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation
35 Logic BIST with Capture-per-Clock Hybrid Test Points
36 Flexible Architecture of Memory BISTs
37 Efficient Implementations of 4-Bit Burst Error Correction for Memories
38 Towards Efficient Modular Adders based on Reversible Circuits
39 Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
40 Design, Implementation and Verification of 32-Bit ALU with VIO
41 All Optical Design of Hybrid Adder Circuit Using Terahertz Optical Asymmetric Demultiplexer
42 A Novel Reversible Synthesis of Array Multiplier
43 Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter
44 FIR filter design based on FPGA
45 An Approach to LUT Based Multiplier for Short Word Length DSP Systems
46 FPGA Implementation of an Improved Watchdog Timer for Safety-critical Applications
47 Chip Design for Turbo Encoder Module for In-Vehicle System
48 BINARY TO GRAY CODE CONVERTER IMPLEMENTATION USING QCA
49 A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)
50 Application of Bit-Serial Arithmetic Units for FPGA Implementation of Convolutional Neural Networks
51 Design and simulation of CRC encoder and decoder using VHDL/verilog
52 Time to Digital Converter Based on a Ring Oscillator with Even Number of Non-Inverting Elements
53 A Channel-Sharable Built-In Self-Test Scheme for Multi-Channel DRAMs
54 Random Number Generation with LFSR Based Stream Cipher Algorithms
55 Characterization of Clock Buffers for On-Chip Inter-Circuit Communication in Xilinx FPGAs
56 Design and Implementation of the Algorithm for RB Multiplication to Derive High-Throughput Digit-Serial Multipliers
57 FPGA Realization of Speech Encryption Based on Modified Chaotic Logistic Map
58 VLSI Implementation of Channel Estimation for Millimeter Wave Beam forming Training
59 Heuristic based Majority/Minority Logic Synthesis for Emerging Technologies
60 A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation
61 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
62 A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA using Chisel HCL
63 Area and Performance Evaluation of Central DMA Controller in Xilinx Embedded FPGA Designs
64 Design of Low Power Multiplierless Linear-Phase FIR Filters
65 Algorithm for Constructing Minimal Representations of Multiple-output Boolean Functions in The Reversible Logic Circuits
66 FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator
67 Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata
68 Design of Power and Area Efficient Approximate Multipliers
69 Low-Power Approximate MAC Unit
70 Efficient Design-for-Test Approach for Networks-on-Chip
71 Integrating BIST techniques for on-line SoC testing
72 A Reliable Strong PUF Based on Switched-Capacitor Circuit
73 Reducing the Hardware Complexity of a Parallel Prefix Adder
74 Research and implementation of hardware algorithms for multiplying binary numbers
75 Division circuits using reversible logic gates
VLSI BACKEND PROJECTS
1 Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique
2 Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
3 Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder
4 Positive Feedback Symmetric Adiabatic Logic against Differential Power Attack
5 Soft-Error Tolerant Design in Near-Threshold-Voltage Computing
6 Stateful Memristor-Based Search Architecture
7 CMOS circuit techniques for Mm –wave communications
8 Approximate Fully Connected Neural Network Generation
9 Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique
10 FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks
11 Analysis of Optimization Techniques for Low Power VLSI Design
12 Low Power GDI ALU Design with Mixed Logic Adder Functionality
13 Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications
14 Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis
15 Fractional-Order Differentiators and Integrators with Reduced Circuit Complexity
16 High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop
17 A Low-Power High-Speed Comparator for Precise Applications
18 High-Density SOT-MRAM Based on Shared Bitline Structure
19 Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM
20 Enabling Fast Process Variation and Fault Simulation Through Macromodelling of Analog Components
21 A SEU/MBU Tolerant SRAM Bit Cell Based on Multi-Input Gate
22 Design of low power magnitude comparator
23 Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications
24 High-performance engineered gate transistor-based compact digital circuits
25 Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation
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VLSI FRONT END PROJECTS
1 Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor
2 A new 16-bit high speed and variable stage carry skip adder
3 Design and Analysis of Multiplier Using Approximate 15-4 Compressor
4 A Review Paper on Design of an Asynchronous Counter Using Novel Reversible SG Gate
5 FPGA Implementation of Memory Design and Testing
6 Double fault tolerant full adder design using fault localization
7 A General Design Framework for Sparse Parallel Prefix Adders
8 An Approach to LFSR-Based X-Masking for Built-In Self-Test
9 Design and Implementation of FFT Pruning algorithm on FPGA
10 A Novel Approach for Reversible Realization of 8- Bit Adder-Subtractor Circuit with Optimized Quantum Cost
11 Timing and Synchronization for explicit FSM based Traffic Light Controllers
12 A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers
13 A Secure Scan Chain Using a Phase Locking System and a Reconfigurable LFSR
14 Efficient Multiply-add Unit Specified for DSPs Utilizing Low-Power Pipeline Modulo 2n+ 1 Multiplier
15 Design of High Speed Carry Select Adder Using Brent Kung Adder
16 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
17 Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
18 Design of Reversible Adders Using A Novel Reversible BKG Gate
19 Low-Power Approximate MAC Unit
20 Comparative study of 16-order FIR filter design using different multiplication techniques
21 Fast Energy Efficient Radix-16 Sequential Multiplier
22 FPGA Realization of Caputo and Grünwald – Letnikov Operators
23 Design of Power and Area Efficient Approximate Multipliers
24 Realization of a hardware generator for the Sum of Absolute Difference component
25 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
26 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
27 LFSR-Based Generation of Multicycle Tests
28 Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata
29 Design of non-restoring divider in quantum dot cellular automata technology
30 MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding
31 Multi Precision Arithmetic Adders
32 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
33 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
34 An Improved Signed Digit Representation Approach for Constant Vector Multiplication
35 A Low Power Reconfigurable LFSR
36 Design of Efficient BCD Adders in Quantum Dot Cellular Automata
37 An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA
38 Design and Analysis of Inexact Floating-Point Adders
39 A Novel Data Format for Approximate Arithmetic Computing
40 Design of low power 5-input Majority Voter in Quantum-dot Cellular Automata with effective Error Resilience
41 High Performance Parallel Decimal Multipliers using Hybrid BCD Codes
42 Implementation of 4x4 Vedic Multiplier using Carry Save Adder in Quantum-Dot Cellular Automata
43 Logic Synthesis in Reversible PLA
44 Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames
45 Quantum-Dot Cellular Automata Divider
46 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
47 Efficient FPGA Mapping of Pipeline SDF FFT Cores
48 Design of Low Cost Latches Based on Reversible Quantum Dot Cellular Automata
49 Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata
50 Random Number Generation with LFSR Based Stream Cipher Algorithms
51 Carry Speculative Adder with Variable Latency for Low Power VLSI
52 Design and Implementation of the Algorithm for RB Multiplication to Derive High- Throughput Digit-Serial Multipliers
53 Design of Low Power Multiplier less Linear-Phase FIR Filters
54 Algorithm for Constructing Minimal Representations of Multiple-output Boolean Functions in The Reversible Logic Circuits
55 Heuristic based Majority/Minority Logic Synthesis for Emerging Technologies
56 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
57 A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation
58 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
59 16 - Bit High speed Modified Booth Multiplier
60 Design And Implementation Of 32 – Bit Reversible Risc Processor Using Xilinx
61 Design And Implementation Of Alu Using Vedic Mathematics Based Multiplication Unit
62 Design And Synthesis Of Reversible Logical Alu Using Reversible Logical Gates
63 Efficient Design And Implementation Of Adders With Reversible Logic
64 Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST
65 Optimized Parity Preserving Full Adder / Full Substractor
VLSI BACKEND PROJECTS
1 Design of 2T XOR Gate Based Full Adder Using GDI Technique
2 Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design
3 Low Power and High Speed Optimized 4-bit Array Multiplier using MOD-GDI Technique
4 A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits
5 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression
6 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
7 Design of a Parallel Self-Timed Adder by Using Transmission Gate Logic Style
8 High-performance engineered gate transistor-based compact digital circuits
9 Design of low power magnitude comparator
10 Design of Level Shifter for Low Power Applications
11 32 bit Power efficient Carry Select Adder Using 4T XNOR gate
12 Delay Analysis for Current Mode Threshold Logic Gate Designs
13 High Performance Ternary Adder using CNTFET
14 New low power adders in Self Resetting Logic with Gate Diffusion Input Technique
15 High Speed Power Efficient Carry Select Adder Design
16 Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications
17 A SEU/MBU Tolerant SRAM Bit Cell Based on Multi-Input Gate
18 Low Power 8-bit ALU Design Using Full Adder and Multiplexer
19 Fault Tolerant Logic Cell FPGA
20 FinFET Based 4-BIT Input XOR/XNOR Logic Circuit
21 Low-Power and Area-Efficient Shift Register Using Pulsed Latches
22 Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing
23 Binary Adder Circuit Design Using Emerging MIGFET Devices
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