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Vlsi Front End Projects For Btech Students

Btech Final year Vlsi Front End Projects for students.Get the list of Btech Vlsi Front End Projects.We will give guidelines about the projects,so students will get the real time knowledge and how to do the projects in a correct manner

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1 Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor
2 A new 16-bit high speed and variable stage carry skip adder
3 Design and Analysis of Multiplier Using Approximate 15-4 Compressor
4 A Review Paper on Design of an Asynchronous Counter Using Novel Reversible SG Gate
5 FPGA Implementation of Memory Design and Testing
6 Double fault tolerant full adder design using fault localization
7 A General Design Framework for Sparse Parallel Prefix Adders
8 An Approach to LFSR-Based X-Masking for Built-In Self-Test
9 Design and Implementation of FFT Pruning algorithm on FPGA
10 A Novel Approach for Reversible Realization of 8- Bit Adder-Subtractor Circuit with Optimized Quantum Cost
11 Timing and Synchronization for explicit FSM based Traffic Light Controllers
12 A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers
13 A Secure Scan Chain Using a Phase Locking System and a Reconfigurable LFSR
14 Efficient Multiply-add Unit Specified for DSPs Utilizing Low-Power Pipeline Modulo 2n+ 1 Multiplier
15 Design of High Speed Carry Select Adder Using Brent Kung Adder
16 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
17 Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
18 Design of Reversible Adders Using A Novel Reversible BKG Gate
19 Low-Power Approximate MAC Unit
20 Comparative study of 16-order FIR filter design using different multiplication techniques
21 Fast Energy Efficient Radix-16 Sequential Multiplier
22 FPGA Realization of Caputo and Grünwald – Letnikov Operators
23 Design of Power and Area Efficient Approximate Multipliers
24 Realization of a hardware generator for the Sum of Absolute Difference component
25 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
26 Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
27 LFSR-Based Generation of Multicycle Tests
28 Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata
29 Design of non-restoring divider in quantum dot cellular automata technology
30 MAC Unit for Reconfigurable Systems Using Multi- Operand Adders with Double Carry-Save Encoding
31 Multi Precision Arithmetic Adders
32 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
33 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
34 An Improved Signed Digit Representation Approach for Constant Vector Multiplication
35 A Low Power Reconfigurable LFSR
36 Design of Efficient BCD Adders in Quantum Dot Cellular Automata
37 An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA
38 Design and Analysis of Inexact Floating-Point Adders
39 A Novel Data Format for Approximate Arithmetic Computing
40 Design of low power 5-input Majority Voter in Quantum-dot Cellular Automata with effective Error Resilience
41 High Performance Parallel Decimal Multipliers using Hybrid BCD Codes
42 Implementation of 4x4 Vedic Multiplier using Carry Save Adder in Quantum-Dot Cellular Automata
43 Logic Synthesis in Reversible PLA
44 Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames
45 Quantum-Dot Cellular Automata Divider
46 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
47 Efficient FPGA Mapping of Pipeline SDF FFT Cores
48 Design of Low Cost Latches Based on Reversible Quantum Dot Cellular Automata
49 Design and Implementation of Arithmetic and Logic Unit (ALU) using Novel Reversible Gates in Quantum Cellular Automata
50 Random Number Generation with LFSR Based Stream Cipher Algorithms
51 Carry Speculative Adder with Variable Latency for Low Power VLSI
52 Design and Implementation of the Algorithm for RB Multiplication to Derive High- Throughput Digit-Serial Multipliers
53 Design of Low Power Multiplier less Linear-Phase FIR Filters
54 Algorithm for Constructing Minimal Representations of Multiple-output Boolean Functions in The Reversible Logic Circuits
55 Heuristic based Majority/Minority Logic Synthesis for Emerging Technologies
56 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
57 A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation
58 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
59 16 - Bit High speed Modified Booth Multiplier
60 Design And Implementation Of 32 – Bit Reversible Risc Processor Using Xilinx
61 Design And Implementation Of Alu Using Vedic Mathematics Based Multiplication Unit
62 Design And Synthesis Of Reversible Logical Alu Using Reversible Logical Gates
63 Efficient Design And Implementation Of Adders With Reversible Logic
64 Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST
65 Optimized Parity Preserving Full Adder / Full Substractor
1 Design of 2T XOR Gate Based Full Adder Using GDI Technique
2 Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design
3 Low Power and High Speed Optimized 4-bit Array Multiplier using MOD-GDI Technique
4 A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits
5 28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression
6 A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
7 Design of a Parallel Self-Timed Adder by Using Transmission Gate Logic Style
8 High-performance engineered gate transistor-based compact digital circuits
9 Design of low power magnitude comparator
10 Design of Level Shifter for Low Power Applications
11 32 bit Power efficient Carry Select Adder Using 4T XNOR gate
12 Delay Analysis for Current Mode Threshold Logic Gate Designs
13 High Performance Ternary Adder using CNTFET
14 New low power adders in Self Resetting Logic with Gate Diffusion Input Technique
15 High Speed Power Efficient Carry Select Adder Design
16 Design of Reversible Full subtractor using new Reversible EVNL gate for Low Power Applications
17 A SEU/MBU Tolerant SRAM Bit Cell Based on Multi-Input Gate
18 Low Power 8-bit ALU Design Using Full Adder and Multiplexer
19 Fault Tolerant Logic Cell FPGA
20 FinFET Based 4-BIT Input XOR/XNOR Logic Circuit
21 Low-Power and Area-Efficient Shift Register Using Pulsed Latches
22 Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing
23 Binary Adder Circuit Design Using Emerging MIGFET Devices
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