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B.Tech Projects
SN PROJECT TITLES ACTIONS
1 Compressor based 8x8 bit Vedic Multiplier using Reversiblelogic
2 Intelligent and Adaptive Traffic Light Controller(IA-TLC) using FPGA
3 Fastest Multiplier Using Two's ComplimentMethod
4 A Low Power Reconfigurable LFSR
5 Error Detection and Correction in SRAM Cell Using DecimalMatrix Code
6 Reverse Converter Design via Parallel-Prefix Adders:Novel Components, Methodology,and Implementations
7 Implementation of 4x4 Vedic Multiplier usingCarry Save Adder in Quantum-Dot CellularAutomata
8 A Novel Implementation of High Speed ModifiedBrent Kung Carry Select Adder
9 CLA based 32-Bit Signed Pipelined Multiplier
10 Design of reversible MAC unit, shift and addmultiplier using PSDRM technique
11 Low-Power Programmable PRPG With TestCompression Capabilities
12 Obfuscating DSP Circuits via High-LevelTransformations
13 Design of High Performance and Low PowerMultiplier using Modified Booth Encoder
14 UART Serial Communication Module Design and SimulationBased on VHDL
15 FPGA Implementation of Scalable MicroprogrammedFIR Filter Architectures using Wallace Tree andVedic Multipliers
16 A Review OnDesign of Improved High Performance of HighValency Ling adder
17 Design of Low Power Reconfigurable Floating PointMultiplier
18 Area Efficient Modified Vedic Multiplier
19 Reliable Low-Power Multiplier Design UsingFixed-Width ReplicaRedundancy Block
20 High Performance Redundant Binary Multiplier
21 An efficient floating point multiplier design for highspeed applications using Karatsuba algorithm andUrdhva-Tiryagbhyam algorithm
22 Implementation of Weighted Test Pattern Generation UsingBuilt in Self Test
23 Efficient Adaptive RLFIR Filter based onDistributed Arithmetic Logic Using Reversible gates
24 Encryption Using Reconfigurable Reversible LogicGate and Its Simulation in FPGAs
25 Design & Analysis of 16 bit RISC ProcessorUsing low Power Pipelining
26 Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic
27 Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic
28 Implementation of High Speed Vedic Multiplierusing Modified Adder
29 Multiple error detection and correction overGF using novel cross parity code
30 Low Power Compressor Based MACArchitecture for DSP Applications
31 Run-time reconfigurable multi-precision floatingpoint multiplier design for high speed, low-powerapplications
32 High-Speed and Energy-Efficient Carry Skip AdderOperating Under a Wide Range ofSupply Voltage Levels
33 Verilog Design of Full Adder Based on ReversibleGates
34 VLSI Design of 64bit × 64bit High PerformanceMultiplier with Redundant Binary Encoding
35 A New programmable ALU architecture for hard-core processor
36 A Method of One-Pass Seed Generationfor LFSR-BasedDeterministic/Pseudo-Random Testing of Static Faults
37 ASIC Design of Signed and Unsigned MultipliersUsing Compressors
38 Intelligent Traffic light controller design using FPGA digest of technical papers
39 Intelligent Traffic light controller design using FPGA digest of technical papers
40 VLSI Design of High Speed Vedic Multiplier forFPGA Implementation
41 Performance Analysis for Different Data-Ratesof Proposed All-Optical Half-Adder and FullAdder Design
42 Smart Traffic Light Control System
43 A Review OnPower Optimized TPG Using LP-LFSR For LowPower BIST
44 Unequal Error Protection Codes Derived fromDouble Error Correction Orthogonal LatinSquare Codes
45 A Novel Realization of Reversible LFSR for itsApplication in Cryptography
46 Low complexity and area efficient reconfigurable multimode interleaver address generator for multi standard radios
47 Low-Cost Multiple Bit Upset Correction inSRAM-Based FPGA Configuration Frames
48 High Performance Reconfigurable Viterbi Decoder Design for Multi-Standard Receiver
49 An Efficient VLSI Architecture of a ReconfigurablePulse-Shaping FIR Interpolation Filterfor Multistandard DUC
50 Fully Reused VLSI Architecture ofFM0/Manchester Encoding Using SOLS Technique for DSRC Applications
51 Fault Tolerant Parallel Filters Basedon Error Correction Codes
52 VLSI Implementation of a Key Distribution Server based Data Security Scheme for RFID system
53 GFCG: Glitch Free Combinational ClockGating Approach in Nanometer VLSI Circuits
54 Power Optimization of Communication System Using Clock Gating Technique
55 Preemptive Built-In Self-Test for In-Field Structural Testing
56 On the Analysis of Reversible Booth’s Multiplier
57 Efficiency constant multiplier in reconfigurable RRC filter
58 Verification of 8x10 Encoder and 10x8 Decoder with 3-bit down ripple counter for USB 3.0 Applications
59 Design of adder and subtractor circuits inmajority logic-based field-coupled QCA nanocomputing
60 Design of area-delay efficient adder based circuits in quantum dotcellular automata
61 BIST Pattern Generation of Functional Broadside Tests for Fixed s27 Benchmark Circuit with Low Power Consumption
62 Implementation of A High Speed Multiplier forHigh-Performance and Low Power Applications
SN PROJECT TITLES ACTIONS
1 Efficient Error Detection and Correction UsingDecimal Matrix Code for Memory Reliability
2 Reducing Dynamic Power Dissipation In Lfsr Using LookAhead Clock Gating And Double Edge Triggering
3 Fpga Based N-Bit Lfsr To Generate RandomSequence Number
4 Implementation Of High Speed Low PowerVedic Multiplier Using Reversible Logic
5 UART Serial Communication Module Design and SimulationBased on VHDL
6 Aging Effect Tolerant Multiprecision Razor-BasedMultiplier
7 Merging of Test Cubes using Test Point Insertionfor Low-Power TestCompaction
8 Radix-8 Modified Booth RecoderForHigh Speed Add-Multiply Operator
9 Design of High Speed Multiplier Using Vedic MathematicsTechnique
10 Convolution and Deconvolution Using VedicMathematics
11 Efficient Computing Techniques using VedicMathematics Sutras
12 Design and Implementation of Partial Reconfigurable FirFilter Using Distributed Arithmetic Architecture
13 Design of Low Power Sequential System Using Multi Bit FLIPFLOP With Data Driven Clock Gating
14 Realisation of Lms Adaptive Algorithm UsingVerilogHdl For Low Complexity
15 Detection and Correction of Multiple Cell Upsets in Static RandomAccess Memories Using Decimal Matrix Code
16 Design of Floating Point Multiplier Using VedicMathematics
17 Approximate Compressors for 32 X 32 BitMultiprecision Multipliers
18 Error Detection and Correction in SRAM Cell Using DecimalMatrix Code
19 Performance Analysis Of Parallel Prefix Adder
20 Improved Error Correction Capability using Parity Matrix Code
21 Analysis Of Various Mcm Algorithms ForReconfigurableRrc Fir Filter
22 Design of ALU using reversible logic based LowPower Vedic Multiplier
23 A Novel Method for Area Efficient N-Bit FullComparator Using Quantum-Dot CellularAutomata
24 A Novel Approach for Parallel CRC Generation forHigh Speed Application
25 An Efficient Design and Implementation of ALU using GatedDiffusion Index
26 Reliability of Memory Storage System UsingDecimal Matrix Code and Meta-Cure
27 Simulation Analysis and Characterization of Low Power andHigh-Speed Digital Circuits
28 On-Chip Comparison based Secure Output ResponseCompactor for Scan-based Attack Resistance
29 Reducing Power Consumption Using Clock GatingTechnique In Flipflop
30 A Novel SOC Design Based on Multi-Bit Flip Flop Design for Reducing Area
31 Review of LP-TPG Using LP-LFSR for Switching Activities
32 Design of reversible MAC unit, shift and addmultiplier using PSDRM technique
33 Purpose of Low-Power Linear Feedback Shift Register (LFSR) byusing Bipartite and Random Injection Method for Low Power BIST
34 Implementation Of TestableReversible Sequential Circuit On FPGA
35 New VlsiBwa Architecture ForFinding The First WMaximum/Minimum Values UsingSorting Algorithms
36 VLSI Implementation of ALU using Reversible Logic with Vedic Mathematics
37 Design Of Compact Reversible Low Power N-Bit BinaryComparator Using Reversible Gates
38 Design A Low Power eight-bit Reversible ParallelBinary Adder/Subtractor
39 Design of Low Power Optimized FilterArchitecture using VLSI Technique
40 Area optimization Technique for Multi-standard DUC
41 Design of Reversible Code Converters forQuantum Computer based Systems
42 Design and FPGA Implementation of Optimized 32- Bit Vedic Multiplier and Square Architectures
43 Implementation of Weighted Test Pattern Generation UsingBuilt in Self-Test
44 FPGA Implementation of an Efficient Vedic Multiplier
45 Implementation of Low Power TPG using LFSRand single input changing generator (SICG) forBIST Application
46 Performance Analysis Of Urdhva AndNikhilam Multiplier
47 A High Speed Binary Floating Point Multiplierusing Dadda Algorithm
48 A Reversible Logic based Power Efficient N*1Multiplexer Design using SRM Gate
49 Design and Implementation of Vedic Algorithm using ReversibleLogic Gates
50 An Approach to Reduce Number of Redundant Bitsused To Overcome Cell Upsets in Memory usingDecimal Matrix Code
51 Low Power Fir Filter Design Using Truncated Multiplier
52 Design and Implementation of Orthogonal Latin SquaresEncoders for Concurrent Error Detection
53 On the Analysis of Reversible Booth’s Multiplier
54 FPGA Implementation of Vedic Floating PointMultiplier
SN PROJECT TITLES ACTIONS
1 High Speed Convolution and Deconvolution Algorithm
2 8 Bit RISC Processor Using Verilog HDL
3 Implementation of high speed low power combinational and sequential circuits using reversible logic
4 Design and estimation of delay power and area for Parallel prefix adders
5 Design and Analysis of Approximate Compressors for Multiplication
6 A Modified Bec Logic Design of High Speed Csla For Low Power And Area Efficient Applications
7 Design and Implementation of Floating Point Multiplier Using Wallace and Dadda Algorithm
8 Design of High Speed Low Power Multiplier Using Nikhilam Sutra with Help of Reversible Logic
9 Design of High Speed Area Efficient Low Power Vedic Multiplier Using Reversible logic gate
10 FPGA Implementation of Single Precision Floating Point Multiplier using High Speed Compressors
11 Low Power 64bit Multiplier Design by Vedic Mathematics
12 An Efficient High Speed Wallace Tree Multiplier
13 Design of High Performance 64 bit MAC Unit
14 A Low Transition Test Pattern Generation Of Multiple Sic Vectors Based On BIST Schemes
15 Test Pattern Generation Using BIST Schemes
16 Modified Hamming Codes to Enhance Short Burst Error Detection in Semiconductor Memories
17 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC
18 Low Power Fir Filter Design Using Truncated Multiplier
19 Low Complexity Digit Serial FIR Filter By Multiple Constant Multiplication Algorithms
20 VLSI Architecture For Optimized Low Power Digit Serial FIR Filter With FPGA
21 Fast FIR Algorithm Based Area Efficient Parallel FIR Digital Filter Structures
22 Analysis of Fast FIR Algorithms based Area Efficient FIR Digital Filters
23 A Novel Fast FIR Algorithm for Area Efficient Parallel FIR Digital Filter Structures Utilizes Symmetric Convolutions
24 Design And Implementation Of An On Chip Permutation Network For Multiprocessor System On Chip
25 Design Of An On Chip Permutation Network For Multiprocessor Soc
26 Design and simulation of 16 Bit UART Serial Communication Module Based on Verilog
27 A Low Power Single Phase Clock Distribution Multiband Network
28 Enhanced Memory Reliability Using Parity Matrix Code
29 FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders
30 Implementing Double Error Correction Orthogonal Latin Squares Codes in Xilinx FPGAs
31 To Test ISCAS 85 C432 27 by Using Built In Generation of Functional Broadside
32 Ancient Indian Vedic Mathematics based 32-BitMultiplier Design for High Speed and Low PowerProcessors
33 Design of Floating Point Arithmetic Logic Unit with Universal Gate
SN PROJECT TITLES ACTIONS
1 Energy efficient code converters by using reversible logic gates
2 An efficient SQRT architecture of Carry Select adder design by Boolean
3 An efficient high speed Wallace tree multiplier
4 Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA
5 Design of High Efficiency Carry Select Adder Using SQRT Technique
6 FPGA based implementation of a double precision IEEE floating point adder
7 LFSR-reseeding scheme for achieving test coverage
8 Optimized architecture for Floating Point computation Unit
9 Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers
10 Sharing Logic for Built-In Generation of Functional Broadside
11 Implementation of cryptographic algorithm on FPGA
12 128-bit carry select adder having less area and delay
13 FPGA implementation high speed vedic multiplier using barrel shifter
14 Improved Design of Low Power TPG Using LPLFSR
15 HICPA:64 bit hybrid low power adder for high performance processors
16 128 bit low power VLSI adder subsystem
17 Parity preserving logic based fault tolerant reversible ALU
18 Efficient concurrent BIST with comparator based response analayzer
19 Area efficient high speed low power multiplier architecture for multirate
20 Used self controllable voltage level techniques to reduce leakage currents
21 Minimization leakage current of full adder using deep sub micron CMOS
22 Normaliation of floating point multiplication using verilog hdl
23 Design and implementation of truncated multipliers for precision improvement
24 Design of high speed hardware efficient 4 bit sfq multiplier
25 Hdl implementation of non restoring division algorithem using high speed
26 Implementation of fixed point square root algorithem on fpga hardware
27 Platform independent customizable UART soft core
28 Design and Implementation of FPGA based High Resolution Digital Pulse
29 Design and implementation of floating point ALU in FPGA
30 Hardware implementation of truncated multiplier based on multiplier
31 Time multiplexed offset carrier QPSK for GNSS.
32 GF(Q) LDPC decoder design for FPGA implementation
33 A high speed and low power VLSI multiplier using redundant binary booth
34 FPGA implementation of booths and baugh wooley multiplier using verilog
35 RTL design and implementation of BPSK modulation at low bit rate
36 Architecture and implementation of a vector/SIMD multiply accumulate
37 32 bit MAC unit design using vedic multiplier
38 Low transition LFSR for bist based application
39 Arbitory density pattern based reduction of testing time in scan-bist
40 An Efficient Interpolation-Based Chase BCH decoder
41 Radix 8 booth encoded modulo multipliers with adaptive delay for high dynamic range residue number system
42 A new VLSI architecture of parallel multiplier accumulator based on radix 2 modified booth algorithm
43 A VLIW vector media compressor with cascaded SIMD ALUs
44 Optimized implementation of FFT processor for OFDM systems
45 Finite state machine based vending machine controller with auto billing features
46 The design of high performance barrel integer adder
47 Architectural level power optimization techniques for multipliers
48 Design of characterization of parallel pre fix adders using FPGA
49 Design and minimization of reversible circuits for a data acquisition and storage system
50 Arithmetic & logic unit (ALU) design using reversible control unit
51 A distinguish between reversible and conventional logic gates
52 Design & implementation of MAC unit using reversible logic
53 An efficient implementation of floating point multiplier
54 Reducing the computation time in (short bit width) two s complement multipliers
55 Fault tolerant variable block carry skip logic (VBCSL) using parity preserving reversible gates
56 Design of a nano metric reversible 4 bit binary counter with parallel load
57 A New Reversible Design of BCD Adder
58 Pipelined Radix 2k Feed forward FFT Architectures
59 Parallel AES Encryption Engines for Many Core Processor Arrays
60 Reverse Circle Cipher for Personal and Network Security
61 A Topology Based Model for Railway Train Control Systems
62 A Novel Transistor Level Realization of Ultra Low Power High Speed Adiabatic Vedic Multiplier
63 Low Power High Throughput and Low Area Adaptive FIR Filter Based on Distributed Arithmetic
64 A New VLSI Architecture of parallel multiplier accumulator based on radix 2 Modified Booth Algorithm
65 Implementation of low cost Bist circuit for Public Key Crypto cores
66 Initialization based Test Pattern generation for Asynchronous circuits
67 Design a low power Booth Multiplier in FPGA
68 Implementation of MAC Unit
69 Design of Uart Transmitter module and Uart Receiver module
70 Verilog code for 3*3 Matrix Multiplication
71 Uart module for Real Time Application
72 Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
73 Design of Locally Clocked Asynchronous Finite State Machines Using Synchronous CAD Tools
74 Implementation of Binary to Floating Point Converter using HDL
75 High Performance and Power Efficient 32 bit Carry Select Adder using Hybrid PTL CMOS Logic Style
76 Implementation and Comparison of Effective Area Efficient Architectures for CSLA
77 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System
78 Design of High Speed Low Power Multiplier using Reversible logic a Vedic Mathematical Approach
79 Design of High Performance 64 bit MAC Unit
80 Enhanced Area Efficient Architecture for 128 bit Modified CSLA
81 VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
82 Optimized Reversible Vedic Multipliers for High Speed Low Power Operations
83 Efficient Approaches to Design a Reversible Floating Point Divider
84 Design a DSP Operations using Vedic Mathematics
85 Adaptive Low Power RTPG for BIST based Test Applications
86 Design and Simulation of UART Serial Communication Module Based on Verilog
87 A New Reversible Design of BCD Adder
88 High Speed VLSI Architecture for General Linear LFSR Structures
89 Data Encryption Algorithm for Secure Communication
90 Built in Self Test Technique for Diagnosis of Delay Faults in Cluster Based Field Programmable Gate Arrays
91 Synthesis and Implementation of UART Using Verilog Codes
92 Power comparison of CMOS And Adiabatic Full Adder Circuits
93 Comments on Low Energy CSMT Carry Generators and Binary Adders
94 FPGA Based Implementation of a Double Precision IEEE Floating Point Adder
96 Design of High Speed Low Power Multiplier using Reversible logic A Vedic Mathematical Approach
97 Novel High Speed Vedic Mathematics Multiplier using Compressors
98 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
99 4 BIT SFQ Multiplier
100 Carry Tree Adder
101 Cordic Processor for Complex DPLL
102 Custom Floating Point Unit Generation
103 Cyclic Redundancy Checker Generator
104 Design of Data Encryption Standard (DES) for Data Encryption
105 Design And Synthesis Of Programmable Logic Block
106 Design Of Reversible Finite Field Arithmetic
107 Design of 16 Point Radix 4 FFT Algorithm
108 Design Of 32 Bit RISC Processor
109 Design of Finite Impulse Response Filter
110 Design Of Radix 2 Butterfly processor to prevent Overflow in The Arithmetic
111 Designing Efficient Online Testable Reversible Adders
112 Fault Secure Encoder 159Floating Point Multiplier
113 Floating Point Vector Coprocessor
114 Floating Point Vector Coprocessor
115 High Performance Complex Number Multiplier Using Booth Wallace Algorithm
116 High Accuracy Fixed Width Modified Booth Multipliers
117 Implementation of Hamming Code
118 LFSR Based Test Generator Synthesis
119 Low Power ALU Design By Ancient Mathematics
120 Parallel Prefix Adders Using FPGAS
121 Design Of Parallel Multiplier Based On RADIX 2 Modified Booth Algorithm
122 Reconfigurable Coprocessor for Redundant Radix 4 Arithmetic
123 Shift Register Based Data Transposition
124 Short Range MIMO Communications
125 Turbo Encoder For LTE Process
126 Universal Asynchronous Receiver Transmitter
127 Very Fast and Low Power Carry Select Adder Circuit
128 Area Delay Power Efficient Fixed Point LMS Adaptive Filter with Low Adaptation Delay
129 Low Power Area Efficient High Speed I O Circuit Techniques
130 Low Power High Throughput and Low Area Adaptive FIR Filter Based on Distributed Arithmetic
131 Smart Reliable Network on Chip
132 Time Based All Digital Technique for Analog Built in Self Test
133 A Low Power Single Phase Clock Distribution using VLSI technology
134 CORDIC based Fast Radix 2 DCT Algorithm
135 Design of Digit Serial FIR Filters Algorithms Architectures and a CAD Tool
136 Design of Low Energy High Performance Synchronous and Asynchronous 64 Point FFT
137 FFT Architectures for Real Valued Signals Based on Radix 2 by 3 & Radix 2 by 4 Algorithms
138 Pipelined Radix 2k Feed forward FFT Architectures
139 An Analytical Latency Model for Networks on Chip
140 Application Driven End to End Traffic Predictions for Low Power NoC Design
141 Low Latency Systolic Montgomery Multiplier for Finite Field GF(2^{m}) Based on Pentanomials
142 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
143 High Throughput Compact Delay Insensitive Asynchronous NOC Router
144 Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm
145 Low Power Digital Signal Processing Using Approximate Adders
146 Comparison of Static and Dynamic Printed Organic Shift Registers
147 A High Performance D Flip Flop Design with Low Power Clocking System using MTCMOS
148 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor
149 Performance Analysis of a New CMOS Output Buffer
150 Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique
151 Asynchronous Design of Energy Efficient Full Adder
152 A Novel High Performance CMOS 1 Bit Full Adder Cell
153 Low Power and Area Efficient Carry Select Adder
154 Digital CMOS Parallel Counter Architecture Based on State Look Ahead Logic
155 Design Low Power 10T Full Adder Using Process and Circuit Techniques
156 A High Speed Low Power Multiplier Using an Advanced Spurious Power Suppression Technique
157 A Framework for Correction of Multi Bit Soft Errors
158 ASIC Design of Complex Multiplier
159 Design and Implementation of Floating Point ALU
160 Design of Data Encryption Standard for Data Encryption
161 Synthesis and Implementation of UART Using Verillog Codes
162 Improved Architectures for a Fused Floating Point Add Subtract Unit
163 Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
164 Design and Implementation of Efficient Systolic Array Architecture
SN PROJECT TITLES ACTIONS
1 Low Power 10 Transistor Full Adder Design Based on Degenerate Pass Transistor
2 Design of 64 Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic
3 Design of low power high speed vlsi adder Subsystem
4 Synthesis and Implementation of UART using verilog Codes
5 HICPA A Hybrid Low Power Adder for High Performance Processors
6 Low Power and Area Efficient Carry Select Adder
7 Design and Implementation of Two Variable Multiplier Using KCM and Vedic
8 Design and Implementation of a High Performance Multiplier using HDL
9 Design of low power and high performance radix 4 multiplier
10 High Speed and Area Efficient Vedic Multiplier
11 Built In Generation of Functional Broadside Tests Using a Fixed Hardware
12 Low power variation aware flipflop
13 High speed Modified Booth Encoder multiplier for signed and unsigned
14 An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
15 High Speed Signed Multiplier for Digital SignalProcessing Applications
16 Accumulator Based 3 Weight Pattern Generation
17 Design of Low Power TPG Using LP LFSR
18 A Real time Face Detection And Recognition System
19 Verilog Implementation of UART with Status Register
20 FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization
21 Design and Implementation of Area optimized AES
22 A Low Power Single Phase Clock Multiband Flexible Divider
23 A Novel All Digital Multichannel Multimode RF Transmitter Using Delta Sigma Modulation
24 Pipelined Parallel FFT Architectures via Folding Transformation
25 An Efficient Architecture for 2D Lifting based Discrete Wavelet Transform
26 Power Efficient Pipelined Reconfigurable Fixed Width Baugh Wooley Multipliers
27 32 bit RISC CPU Based on MIPS High Speed Hardware Implementation of 1D DCT IDCT
28 Efficient FPGA implementation of convolution
29 High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures
30 Design and Implementation of a 64 bit RISC Processor using Verilog HDL
31 Design and Implementation of Wi Fi MAC Transmit Protocol using VHDL
32 High speed parallel architecture for cyclic convolution based on FNT
33 Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
34 A Memory efficient Huffman Decoding Algorithm
35 Minimization of Switching Activities of Partial Products for Designing Low Power Multipliers
36 A New High Speed Architecture for Reed Solomon Decoder
37 The study of soc architecture design based on 32 bit embedded risc processor
38 An efficient fpga implementation of the advanced encryption standard algorithm
39 High speed modified booth encoder multiplier for signed and unsigned numbers
40 A new approach for high performance andefficient design of cordic processor
41 Fpga implementation of binary coded decimal Digit adders and multipliers
42 A high throughput configurable fft processor for wlan and wimax protocols
43 Design & implementation of floating point alu on a fpga processor
44 Design and implementation of low power fft ifft Processor for wireless communication
45 A novel approach for parallel CRC generation for high speed applications
46 An On Chip Delay Measurement Technique Using Signature Registers For Small Delay Defect Detection
47 Single Cycle Access Structure For Logic Test
48 A Low Power Single Phase Clock Multiband Flexible Divider ON MODULO 2n 1 ADDER DESIGN
49 Implementation of a Flexible and Synthesizable FFT Processor
50 A Multi Agent Framework for Thermal Aware Task Migration in Many Core Systems
51 A High Precision On Chip Path Delay Measurement Architecture
52 Full Fault Resilience and Relaxed Synchronization Requirements at the Cache Memory Interface
53 Location Cache Design and Performance Analysis for Chip Multiprocessors
54 Cusnoc Fast Full Chip Custom noc Generation
55 An Analytical Latency Model for Networks on Chip
56 Combined Architecture Algorithm Approach to Fast FPGA Routing
57 Addressing Transient and Permanent Faults in noc With Efficient Fault Tolerant Deflection Router
58 Semi Serial On Chip Link Implementation for Energy Efficiency and High Throughput
59 Dual Layer Adaptive Error Control for Network on Chip Links
60 A Variation Tolerant Current Mode Signaling Scheme for On Chip Interconnects
61 Reconfigurable Routers for Low Power and High Performance
62 Throughput Resource Efficient Reconfigurable Processor for Multimedia Applications
63 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
64 All Digital Wide Range Precharge Logic % Duty Cycle Corrector
65 A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
66 Low Power Pulse Triggered Flip Flop Design With Conditional Pulse Enhancement Scheme
67 Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
68 Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
69 Efficient Majority Logic Fault Detection With Difference Set Codes for Memory Applications
70 Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications
71 Unified Architecture for Reed Solomon Decoder Combined With Burst Error Correction
72 Precision Aware Self Quantizing Hardware Architectures for the Discrete Wavelet Transform
73 Jointly Designed Architecture Aware LDPC Convolutional Codes and Memory Based Shuffled Decoder Architecture
74 Area Time Efficient Scaling Free CORDIC Using Generalized Micro Rotation Selection
75 CORDIC Designs for Fixed Angle of Rotation
76 Low Cost Self Test Techniques for Small rams in socs Using Enhanced IEEE 1500 Test Wrappers
77 Soft Error Resilient fpgas Using Built In D Hamming Product Code
78 Built In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
79 A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
80 An Area Effective Parity Based Fault Detection Technique for fpgas
81 Robust Secure Scan Design Against Scan Based Differential Cryptanalysis
82 A Pipeline VLSI Architecture for Fast Computation of the 2D Discrete Wavelet Transform
83 A Novel Filter Bank Multicarrier Scheme to Mitigate the Intrinsic Interference Application to MIMO Systems
84 A Wideband Digital RF Receiver Front End Employing a New Discrete Time Filter for m WiMAX
85 Cooperative Beam forming for Cognitive Radio Networks A Cross Layer Design
86 Good Synchronization Sequences for Permutation Codes
87 High Throughput Soft Output MIMO Detector Based on Path Preserving Trellis Search Algorithm
88 Low Complexity Iterative Channel Estimation for Turbo Receivers
89 Novel Interpolation and Polynomial Selection for Low Complexity Chase Soft Decision Reed Solomon Decoding
90 Synthesis and Array Processor Realization of a 2D IIR Beam Filter for Wireless Applications
91 The Design of Hybrid Asymmetric FIR Analog Pulse Shaping Filters Against Receiver Timing Jitter
92 Transmission of 4 ASK Optical Fast OFDM With Chromatic Dispersion Compensation
93 State Space Frequency Domain Adaptive Filtering for Nonlinear Acoustic Echo Cancellation
94 Telephone Channel Compensation in Speaker Verification Using a Polynomial Approximation in the Log Filter Domain
95 A Fast Cryptography Pipelined Hardware developed in FPGA with Verilog HDL
96 A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits
97 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
98 A Low Power Low Cost Design of Primary Synchronization Signal Detection
99 A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS LMS Adaptive Filter
100 Area Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
101 Area Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
102 Design and Simulation of 32 Point FFT Using Radix 2 Algorithm for FPGA Implementation
103 Design of Digit Serial FIR Filters Algorithms Architectures and a CAD Tool
104 Pipelined Parallel FFT Architectures via Folding Transformation
105 Platform Independent Customizable UART Soft Core
106 Design and Implementation of a New Multilevel Inverter Topology
107 Digital Filters for Fast Harmonic Sequence Component Separation 3Ph
108 A Filter Bank and a Self Tuning Adaptive Filter for the Harmonic and Inter harmonic Estimation in Power Signals
109 Design of Low Voltage Low Power Operational Amplifier
110 Low Power Pulse Triggered Flip-Flop Design With Conditional Pulse Enhancement Scheme
111 Low Swing Differential Conditional Capturing Flip Flop for LC Resonant Clock Distribution Networks
112 Design & implementation of floating point ALU on a FPGA processor
113 Finite State Machine Motion Controller Servo Drives
114 Design and implementation of fault tolerant soft processors on FPGAs
115 MPSoC design approach of FPGA based controller for induction motor drive
116 VHDL Implementation of UART with Status Register
117 Power quality measurement system using FPGAs
118 Study of navigation methods based on embedded dual encoder
119 FPGA system on chip solution for a field oriented hybrid stepper motor control
120 FPGA Implementation of 8 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial using VHDL
121 Optimization of Microcode Built In Self Test By Enhanced Faults Coverage for Embedded Memory
122 Low Power and Area Efficient Carry Select Adder
123 A High Performance D Flip Flop Design with Low Power Clocking System using MTCMOS Technique
124 A Novel Architecture for VLSI Implementation of RSA Cryptosystem
125 The LUT SR family of uniform random Number generators for FPGA architectures
126 Extending the effective throughput of NOCS with Distributed shared buffer routers
127 Algorithm and the Optimal Finite Wordlength FIR Design
128 Channels with Single User Decoding
129 VLSI Implementation of Scalable Encryption Algorithm for Different Text and Processor Size
130 Designing of Low Power VLSI Circuits using Non Clocked Logic Style
131 Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility Speed and Complexity Trade Offs
132 The complexity of VLSI power delay optimization by interconnect resizing
133 Implementation of LFSR Counter Using CMOS VLSI Technology
134 Channel Height Estimation for VLSI Design
135 Efficient Mathematical Model on VLSI Circuit Partitioning
136 Area Efficient and Low Power VLSI Architecture of Min Sum LDPC Codes using Wave Pipelining
137 High Performance VLSI Architecture for FIR Filter using on the Fly Conversion Multiplier
138 VLSI Micro Architectures for High Radix Crossbars
139 A New Vlsi Architecture Of Parallel Multiplier Based On Radix 4 Modified Booth Algorithm Using Vhdl
140 Analysis of high performance vlsi for telecommunication data
141 Efficient Majority Logic Fault Detection With Difference Set Codes for Memory Applications
142 FFT Implementation with Fused Floating Point Operations
143 High Speed Architectures for Multiplication Using Reordered Normal Basis
144 Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
145 A High Accuracy Adaptive Conditional Probability Estimator for Fixed Width Booth Multipliers
146 Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
147 Area Time Efficient Scaling Free CORDIC Using Generalized Micro Rotation Selection
148 Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
149 Design and Simulation of 32 Point FFT Using Radix 2 Algorithm for FPGA Implementation
150 A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
151 Design of Modified Low Power Booth Multiplier
152 Design of 64 bit low power parallel prefix vlsi adder for high speed Arithmetic circuits
153 Implementation of convolution encoder and viterbi decoder using verilog Hdl
154 FPGA Hardware of the LSB Steganography Method
155 BIST using genetic algorithm for error detection and correction
156 Optimizing Floating Point Units in Hybrid FPGAs
157 Bayesian Equalization for LDPC Channel Decoding
158 Low Complexity Soft Decoding of Huffman Codes and Iterative Joint Source Channel Decoding
159 Human Gait Modeling Using a Genetic Fuzzy Finite State Machine
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