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Front End Research Projects
Sl.No Project Code DSP Core Projects Action
1 TVREFE19_27 Digit-serial Versatile Multiplier Based On A Novel Block Recombination Of The Modified Overlap-free Karatsuba Algorithm View Details
2 TVREFE19_14 A High-performance And Energy-efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits View Details
3 TVREFE19_38 A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory View Details
4 TVREFE19_20 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
5 TVREFE19_42 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
6 TVREFE19_02 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
7 TVREFE19_22 A High-flexible Low-latency Memory-based FFT Processor For 4G, WLAN, And Future 5G View Details
8 TVREFE19_23 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
9 TVREFE19_50 High Performance Multiplier Less Serial Pipelined VLSI Architecture For Real-valued FFT View Details
10 TVREFE19_49 Feed Forward-cut Set-free Pipe Lined Multiply–accumulate Unit For The Machine Learning Accelerator View Details
11 TVREFE19_05 An Efficient VLSI Architecture For Convolution Based DWT Using MAC View Details
12 TVREFE19_53 Reconfigurable Radix-2k×3 Feed forward FFT Architectures View Details

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