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Front End Research Projects
Sl.No Project Code Communications and Crypto Core Projects Action
1 TVREFE19_55 Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field View Details
2 TVREFE19_16 A Probabilistic Parallel Bit-flipping Decoder For Low-density Parity-check Codes View Details
3 TVREFE19_60 Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA View Details
4 TVREFE19_19 Error Detection And Correction In SRAM Emulated TCAMs View Details
5 TVREFE19_65 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
6 TVREFE19_04 A Double Error Correction Code For 32-bit Data Words With Efficient Decoding View Details
7 TVREFE19_71 MAES: Modified Advanced Encryption Standard for Resource Constraint Environments View Details
8 TVREFE19_13 A Decoder For Short Bch Codes With High Decoding Efficiency And Low Power For Emerging Memories View Details
9 TVREFE19_41 An Area-efficient On-chip Memory System For Massive MIMO Using Channel Data Compression View Details
10 TVREFE19_45 Design Of Low-power Non-binary Ldpc Decoder Exploiting Dram Refresh Rate Over-scaling View Details
11 TVREFE19_46 Detection Of Limited Magnitude Errors In Emerging Multilevel Cell Memories By One-bit Parity (obp) Or Two-bit Parity (tbp) View Details
12 TVREFE19_40 A Solution For Ultra-low Bit-error-rate Interface Of Superconductor-semiconductor By Using An Error-correction-code Encoder View Details
13 TVREFE19_54 Two Bit Overlap: A Class Of Double Error Correction One Step Majority Logic Decodable Codes View Details

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