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Front End Major Projects
Sl.No Project Code Arithmetic Core Projects Action
1 TVMAFE18 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
2 TVMAFE25 Concurrent Error Detectable Carry Select Adder With Easy Testability View Details
3 TVMAFE60 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
4 TVMAFE68 Performance Evaluation Of Fixed-point Array Multipliers On Xilinx FPGAs View Details
5 TVMAFE11 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
6 TVMAFE26 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
7 TVMAFE42 Fast Hub Floating-point Adder For FPGA View Details
8 TVMAFE53 A Design And Implementation Of Montgomery Modular Multiplier View Details
9 TVMAFE63 Design Of Delay Efficient Hybrid Adder For High Speed Applications View Details
10 TVMAFE01 A Low-power High-speed Accuracy-controllable Approximate Multiplier Design View Details
11 TVMAFE21 A Combined Arithmetic-high-level Synthesis Solution To Deploy Partial Carry-save Radix-8 Booth Multipliers In Datapaths View Details
12 TVMAFE43 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
13 TVMAFE56 A Hardware-efficient Logarithmic Multiplier With Improved Accuracy View Details
14 TVMAFE02 Design And Evaluation Of Approximate Logarithmic Multipliers For Low Power Error-tolerant Applications View Details
15 TVMAFE16 Analysis, Modeling And Optimization Of Equal Segment Based Approximate Adders View Details
16 TVMAFE24 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
17 TVMAFE28 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
18 TVMAFE65 Factorized Carry Look Ahead Adder View Details
19 TVMAFE86 Design and Analysis of Majority Logic Based Approximate Adders and Multipliers View Details
20 TVMAFE09 Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers View Details
21 TVMAFE30 Tunable Floating-point Adder View Details
22 TVMAFE35 Rounding Technique Analysis For Power-area & Energy Efficient Approximate Multiplier Design View Details
23 TVMAFE52 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
24 TVMAFE20 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
25 TVMAFE32 Low-power High-accuracy Approximate Multiplier Using Approximate High- Order Compressors View Details
26 TVMAFE71 Implementation Of Addition And Subtraction Operations In Multiple Precision Arithmetic View Details
27 TVMAFE14 Tosam: An Energy-efficient Truncation- And Rounding-based Scalable Approximate Multiplier View Details
28 TVMAFE27 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
29 TVMAFE33 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
30 TVMAFE64 Energy Efficient Speed-independent 64-bit Fused Multiply-add Unit* View Details
31 TVMAFE75 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
32 TVMAFE34 Modified Binary Multiplier Circuit Based On Vedic Mathematics View Details
33 TVMAFE50 16 Bit Power Efficient Carry Select Adder View Details
34 TVMAFE57 A Low Power Binary Square Rooter Using Reversible Logic View Details
35 TVMAFE89 Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders View Details

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