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Front End Major Projects
Sl.No Project Code
Arithmetic Core Projects
Action
1 TVMAFE14 Tosam: An Energy-efficient Truncation- And Rounding-based Scalable Approximate Multiplier View Details
2 TVMAFE11 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
3 TVMAFE20 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
4 TVMAFE26 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
5 TVMAFE32 Low-power High-accuracy Approximate Multiplier Using Approximate High- Order Compressors View Details
6 TVMAFE53 A Design And Implementation Of Montgomery Modular Multiplier View Details
7 TVMAFE63 Design Of Delay Efficient Hybrid Adder For High Speed Applications View Details
8 TVMAFE71 Implementation Of Addition And Subtraction Operations In Multiple Precision Arithmetic View Details
9 TVMAFE21 A Combined Arithmetic-high-level Synthesis Solution To Deploy Partial Carry-save Radix-8 Booth Multipliers In Datapaths View Details
10 TVMAFE27 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
11 TVMAFE33 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
12 TVMAFE56 A Hardware-efficient Logarithmic Multiplier With Improved Accuracy View Details
13 TVMAFE64 Energy Efficient Speed-independent 64-bit Fused Multiply-add Unit* View Details
14 TVMAFE02 Design And Evaluation Of Approximate Logarithmic Multipliers For Low Power Error-tolerant Applications View Details
15 TVMAFE16 Analysis, Modeling And Optimization Of Equal Segment Based Approximate Adders View Details
16 TVMAFE24 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
17 TVMAFE28 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
18 TVMAFE34 Modified Binary Multiplier Circuit Based On Vedic Mathematics View Details
19 TVMAFE50 16 Bit Power Efficient Carry Select Adder View Details
20 TVMAFE57 A Low Power Binary Square Rooter Using Reversible Logic View Details
21 TVMAFE65 Factorized Carry Look Ahead Adder View Details
22 TVMAFE18 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
23 TVMAFE25 Concurrent Error Detectable Carry Select Adder With Easy Testability View Details
24 TVMAFE30 Tunable Floating-point Adder View Details
25 TVMAFE35 Rounding Technique Analysis For Power-area & Energy Efficient Approximate Multiplier Design View Details
26 TVMAFE52 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
27 TVMAFE60 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
28 TVMAFE68 Performance Evaluation Of Fixed-point Array Multipliers On Xilinx FPGAs View Details
29 TVMAFE42 Fast Hub Floating-point Adder For FPGA View Details
30 TVMAFE01 A Low-power High-speed Accuracy-controllable Approximate Multiplier Design View Details
31 TVMAFE43 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
32 TVMAFE75 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
33 TVMAFE09 Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers View Details
Front End Major Projects
Sl.No Project Code
Testing Projects
Action
1 TVMAFE67 On Cyclic Scan Integrity Tests For EDT-based Compression View Details
2 TVMAFE40 Chaos-based Bitwise Dynamical Pseudorandom Number Generator On FPGA View Details
3 TVMAFE70 Power Estimation Of Embedded SRAMs Using BIST Algorithms View Details
4 TVMAFE48 An Analysis Of DCM-based True Random Number Generator View Details
5 TVMAFE55 Design And Implementation Of Low-power High-throughput PRNGs For Security Applications View Details
6 TVMAFE77 Study On Early Capture Based VLSI Aging Monitoring Techniques View Details
7 TVMAFE78 A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA View Details
Front End Major Projects
Sl.No Project Code
FPGA Applications Projects
Action
1 TVMAFE69 Performance Evaluation Of Fixed-point Array Multipliers On Xilinx FPGAs View Details
2 TVMAFE61 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
3 TVMAFE08 A Low-power High-speed Accuracy-controllable Approximate Multiplier Design View Details
4 TVMAFE79 Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA View Details
5 TVMAFE41 Fast Hub Floating-point Adder For FPGA View Details
6 TVMAFE83 FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator View Details
Front End Major Projects
Sl.No Project Code
Finite State Machines Projects
Action
1 TVMAFE66 FSM Based High Speed VLSI Architecture For DBUTVF Algorithm View Details
Front End Major Projects
Sl.No Project Code
Cadence Oriented Projects
Action
1 TVMAFE31 Tunable Floating-point Adder View Details
2 TVMAFE62 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
3 TVMAFE10 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
4 TVMAFE47 A Data-flow Methodology For Accelerating FFT View Details
5 TVMAFE12 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
6 TVMAFE49 An Analysis Of DCM-based True Random Number Generator View Details
7 TVMAFE29 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
8 TVMAFE54 A Design And Implementation Of Montgomery Modular Multiplier View Details
Front End Major Projects
Sl.No Project Code
Matlab Applications Projects
Action
1 TVMAFE85 Image and Video Processing Applications Using Xilinx System Generator View Details
2 TVMAFE80 Design of visible light communication with DCT and M-Ary PAM in Xilinx System Generator View Details
3 TVMAFE81 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
4 TVMAFE84 FPGA Implementation of Matrix-Vector Multiplication Using Xilinx System Generator View Details
Front End Major Projects
Sl.No Project Code
QCA nano Technology Projects
Action
1 TVMAFE06 Design Of Majority Logic (ML) Based Approximate Full Adders View Details
2 TVMAFE39 Design Of An Efficient Multilayer Arithmetic Logic Unit In Quantum-dot Cellular Automata (QCA) View Details
3 TVMAFE44 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
Front End Major Projects
Sl.No Project Code
Communications Projects
Action
1 TVMAFE05 A Double Error Correction Code For 32-bit Data Words With Efficient Decoding View Details
2 TVMAFE59 A New Logic For Implementation Of Digital Error Correction Block View Details
3 TVMAFE15 A Probabilistic Parallel Bit-flipping Decoder For Low-density Parity-check Codes View Details
4 TVMAFE72 Low Power Karnaugh Map Approximate Adder For Error Compensation In Loop Accumulations View Details
5 TVMAFE17 Error Detection And Correction In SRAM Emulated TCAMs View Details
6 TVMAFE58 Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field View Details
7 TVMAFE82 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
8 TVMAFE76 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
Front End Major Projects
Sl.No Project Code
DSP Core Projects
Action
1 TVMAFE19 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
2 TVMAFE38 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
3 TVMAFE03 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
4 TVMAFE22 A High-flexible Low-latency Memory-based FFT Processor For 4G, WLAN, And Future 5G View Details
5 TVMAFE23 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
6 TVMAFE46 A Data-flow Methodology For Accelerating FFT View Details
7 TVMAFE13 A High-performance And Energy-efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits View Details
8 TVMAFE37 A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory View Details
9 TVMAFE51 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
10 TVMAFE73 Low-complexity Continuous-flow Memory-based FFT Architectures For Real-valued Signals View Details
11 TVMAFE45 Reconfigurable Radix-2k×3 Feed forward FFT Architectures View Details
12 TVMAFE07 A 4096-point Radix-4 Memory-based FFT Using DSP Slices View Details
Back End Major Projects
Sl.No Project Code
Transistor Logic Projects
Action
1 TVMABE01 Design Of Area-efficient And Highly Reliable Rhbd 10t Memory Cell For Aerospace Applications View Details
2 TVMABE07 Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique For On-chip Digital Filter Applications View Details
3 TVMABE18 A 7t Security Oriented SRAM Bitcell View Details
4 TVMABE09 Design Of Area Efficient And Low Power 4-bit Multiplier Based On Full- Swing GDI Technique View Details
5 TVMABE03 Low-power And Fast Full Adder By Exploring New XOR And XNOR Gates View Details
6 TVMABE10 Designing Efficient Circuits Based On Runtime-reconfigurable Field-effect Transistors View Details
7 TVMABE41 Design Of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder View Details
8 TVMABE05 A Very Compact CMOS Analog Multiplier For Application In CNN Synapses View Details
9 TVMABE25 Analysis Of 1- Bit Full Adder Using Different Techniques In Cadence 45nm Technology View Details
10 TVMABE26 Seda - Single Exact Dual Approximate Adders For Approximate Processors View Details
11 TVMABE37 Power Efficient Design Of Adiabatic Approach For Low Power VLSI Circuits View Details
12 TVMABE19 Energy Efficient Single-ended 6T SRAM For Multimedia Applications View Details
13 TVMABE28 Analysis Of Adiabatic Flip-flops For Ultra Low Power Applications View Details
14 TVMABE39 Low Power Approximate Unsigned Divider Design Using Gate Diffusion Input Logic View Details
15 TVMABE20 Hybrid Logical Effort For Hybrid Logic Style Full Adders In Multistage Structures View Details
16 TVMABE30 Power-delay-product, Area And Threshold-loss Analysis Of CMOS Full Adder Circuits View Details
17 TVMABE14 Parametric And Functional Degradation Analysis Of Complete 14-nm FinFET SRAM View Details
18 TVMABE33 Power Reduction In Domino Logic Using Clock Gating In 16nm CMOS Technology View Details
Back End Major Projects
Sl.No Project Code
Low Power VLSI Projects
Action
1 TVMABE36 Design Of Area Efficient And Low Power 4-bit Multiplier Based On Full Swing GDI Technique View Details
2 TVMABE04 Low-power And Fast Full Adder By Exploring New XOR And XNOR Gates View Details
3 TVMABE08 Design Of Area Efficient And Low Power 4-bit Multiplier Based On Full- Swing GDI Technique View Details
4 TVMABE16 Power Efficient And Reliable Nonvolatile TCAM With Hi-PFO And Semi-complementary Driver View Details
5 TVMABE22 A 12t Low-power Standard-cell Based SRAM Circuit For Ultra-low-voltage Operations View Details
6 TVMABE38 Design Of Low Power ECRL Based Power Gated 4:2 Compressor View Details
7 TVMABE27 Analysis Of Adiabatic Flip-flops For Ultra Low Power Applications View Details
8 TVMABE13 Parametric And Functional Degradation Analysis Of Complete 14-nm FinFET SRAM View Details
9 TVMABE32 Power Reduction In Domino Logic Using Clock Gating In 16nm CMOS Technology View Details
Back End Major Projects
Sl.No Project Code
Cadence Oriented Projects
Action
1 TVMABE24 Analysis Of 1- Bit Full Adder Using Different Techniques In Cadence 45nm Technology View Details
2 TVMABE35 Design Of Area Efficient And Low Power 4-bit Multiplier Based On Full Swing GDI Technique View Details
3 TVMABE40 Design Of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder View Details
4 TVMABE06 A Very Compact CMOS Analog Multiplier For Application In CNN Synapses View Details
5 TVMABE11 Designing Efficient Circuits Based On Runtime-reconfigurable Field-effect Transistors View Details
6 TVMABE34 Delay Optimization Of 4-bit ALU Designed In FS-GDI Technique View Details
7 TVMABE12 Parametric And Functional Degradation Analysis Of Complete 14-nm FinFET SRAM View Details
8 TVMABE02 Design Of Area-efficient And Highly Reliable Rhbd 10t Memory Cell For Aerospace Applications View Details
9 TVMABE15 Power Efficient And Reliable Nonvolatile TCAM With Hi-PFO And Semi-complementary Driver View Details
10 TVMABE29 Power-delay-product, Area And Threshold-loss Analysis Of CMOS Full Adder Circuits View Details
11 TVMABE31 Power Reduction In FinFET Half Adder Using SVL Technique In 32nm Technology View Details
12 TVMABE21 A 12t Low-power Standard-cell Based SRAM Circuit For Ultra-low-voltage Operations View Details
13 TVMABE17 A 7t Security Oriented SRAM Bitcell View Details
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