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Minor Projects
Sl.No Project Code
Projects
Action
1 TVMI07 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
2 TVMI08 Modified Binary Multiplier Circuit Based On Vedic Mathematics View Details
3 TVMI02 Design Of Majority Logic (ML) Based Approximate Full Adders View Details
4 TVMI06 Low-power High-accuracy Approximate Multiplier Using Approximate High- Order Compressors View Details
5 TVMI10 16 Bit Power Efficient Carry Select Adder View Details
6 TVMI03 A Low-power Yet High-speed Configurable Adder For Approximate Computing View Details
7 TVMI11 Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor View Details
8 TVMI15 A Low Power Reconfigurable LFSR View Details
9 TVMI19 Design of 2T XOR Gate Based Full Adder Using GDI Technique View Details
10 TVMI23 An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA View Details
11 TVMI27 Chip Design for Turbo Encoder Module for In-Vehicle System View Details
12 TVMI31 Image and Video Processing Applications Using Xilinx System Generator View Details
13 TVMI04 Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers View Details
14 TVMI12 Design and Analysis of Multiplier Using Approximate 15-4 Compressor View Details
15 TVMI16 A Novel Data Format for Approximate Arithmetic Computing View Details
16 TVMI20 Design of low power magnitude comparator View Details
17 TVMI24 High Speed Efficient Multiplier Design using Reversible Gates View Details
18 TVMI28 Binary to Gray Code converter implementation using QCA View Details
19 TVMI01 Low Power 4-bit Arithmetic Logic Unit Using Full-swing GDI Technique View Details
20 TVMI05 Efficient FIR Filter Design Using Booth Multiplier For VLSI Applications View Details
21 TVMI09 Performance Analysis Of Wallace Tree Multiplier With Kogge Stone Adder Using 15-4 Compressor View Details
22 TVMI13 Design of High Speed Carry Select Adder Using Brent Kung Adder View Details
23 TVMI17 Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression View Details
24 TVMI21 Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique View Details
25 TVMI25 Efficient Implementations of 4-Bit Burst Error Correction for Memories View Details
26 TVMI29 Design and simulation of CRC encoder and decoder using VerilogHDL View Details
27 TVMI14 Low-Power Approximate MAC Unit View Details
28 TVMI18 Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error View Details
29 TVMI22 A Simple Yet Efficient Accuracy- Configurable Adder Design View Details
30 TVMI26 Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter View Details
31 TVMI30 Fractional-Order Differentiators and Integrators with Reduced Circuit Complexity View Details
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