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Front End Research Projects
Sl.No Project ID
Arithmetic Core Projects
Action
1 TVREFE19_21 A Combined Arithmetic-high-level Synthesis Solution To Deploy Partial Carry-save Radix-8 Booth Multipliers In Datapaths View Details
2 TVREFE19_24 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
3 TVREFE19_30 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
4 TVREFE19_01 Design And Evaluation Of Approximate Logarithmic Multipliers For Low Power Error-tolerant Applications View Details
5 TVREFE19_15 Tosam: An Energy-efficient Truncation- And Rounding-based Scalable Approximate Multiplier View Details
6 TVREFE19_25 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
7 TVREFE19_31 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
8 TVREFE19_17 Analysis, Modeling And Optimization Of Equal Segment Based Approximate Adders View Details
9 TVREFE19_09 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
10 TVREFE19_29 Design Of Fsm-based Function With Reduced Number Of States In Integral Stochastic Computing View Details
11 TVREFE19_11 Low-power Approximate Unsigned Multipliers With Configurable Error Recovery View Details
12 TVREFE19_07 Design Of Approximate Radix-4 Booth Multipliers For Error-tolerant Computing View Details
13 TVREFE19_18 Block-based Carry Speculative Approximate Adder For Energy-efficient Applications View Details
14 TVREFE19_48 Fast Hub Floating-point Adder For FPGA View Details
15 TVREFE19_67 A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA View Details
16 TVREFE19_36 A Division-free Toom-cook Multiplication Based Montgomery Modular Multiplication View Details
17 TVREFE19_26 Digit-serial Versatile Multiplier Based On A Novel Block Recombination Of The Modified Overlap-free Karatsuba Algorithm View Details
Front End Research Projects
Sl.No Project ID
DSP Core Projects
Action
1 TVREFE19_38 A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory View Details
2 TVREFE19_20 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
3 TVREFE19_42 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
4 TVREFE19_02 An Area Efficient 1024-point Low Power Radix-22 Fft Processor With Feed-forward Multiple Delay Commutators View Details
5 TVREFE19_22 A High-flexible Low-latency Memory-based FFT Processor For 4G, WLAN, And Future 5G View Details
6 TVREFE19_23 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
7 TVREFE19_14 A High-performance And Energy-efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits View Details
8 TVREFE19_05 An Efficient VLSI Architecture For Convolution Based DWT Using MAC View Details
9 TVREFE19_27 Digit-serial Versatile Multiplier Based On A Novel Block Recombination Of The Modified Overlap-free Karatsuba Algorithm View Details
10 TVREFE19_49 Feed Forward-cut Set-free Pipe Lined Multiply–accumulate Unit For The Machine Learning Accelerator View Details
11 TVREFE19_50 High Performance Multiplier Less Serial Pipelined VLSI Architecture For Real-valued FFT View Details
12 TVREFE19_53 Reconfigurable Radix-2k×3 Feed forward FFT Architectures View Details
Front End Research Projects
Sl.No Project ID
Communications and Crypto Core Projects
Action
1 TVREFE19_19 Error Detection And Correction In SRAM Emulated TCAMs View Details
2 TVREFE19_04 A Double Error Correction Code For 32-bit Data Words With Efficient Decoding View Details
3 TVREFE19_16 A Probabilistic Parallel Bit-flipping Decoder For Low-density Parity-check Codes View Details
4 TVREFE19_55 Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field View Details
5 TVREFE19_13 A Decoder For Short Bch Codes With High Decoding Efficiency And Low Power For Emerging Memories View Details
6 TVREFE19_46 Detection Of Limited Magnitude Errors In Emerging Multilevel Cell Memories By One-bit Parity (obp) Or Two-bit Parity (tbp) View Details
7 TVREFE19_65 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
8 TVREFE19_54 Two Bit Overlap: A Class Of Double Error Correction One Step Majority Logic Decodable Codes View Details
9 TVREFE19_71 MAES: Modified Advanced Encryption Standard for Resource Constraint Environments View Details
10 TVREFE19_40 A Solution For Ultra-low Bit-error-rate Interface Of Superconductor-semiconductor By Using An Error-correction-code Encoder View Details
11 TVREFE19_41 An Area-efficient On-chip Memory System For Massive MIMO Using Channel Data Compression View Details
12 TVREFE19_45 Design Of Low-power Non-binary Ldpc Decoder Exploiting Dram Refresh Rate Over-scaling View Details
13 TVREFE19_60 Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA View Details
Front End Research Projects
Sl.No Project ID
Design for Testability Projects
Action
1 TVREFE19_03 A High Performance Scan Flip-flop Design For Serial And Mixed Mode Scan Test View Details
2 TVREFE19_32 Automatic Test Pattern Generation For Timing Verification And Delay Testing Of Rsfq Circuits View Details
3 TVREFE19_35 A Low-power Parallel Architecture For Linear Feedback Shift Registers View Details
4 TVREFE19_33 On-chip Self-test Methodology With All Deterministic Compressed Test Patterns Recorded In Scan Chains View Details
5 TVREFE19_57 FPGA-based True Random Number Generation Using Programmable Delays In Oscillator-rings View Details
6 TVREFE19_57 A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA View Details
7 TVREFE19_47 Efficient Design-for-test Approach For Networks-on-chip View Details
8 TVREFE19_51 Modified Dual-CLCG Method And Its VLSI Architecture For Pseudorandom Bit Generation View Details
9 TVREFE19_56 FPGA-based True Random Number Generation Using Programmable Delays In Oscillator-rings View Details
Front End Research Projects
Sl.No Project ID
FPGA Applications Projects
Action
1 TVREFE19_08 Efficient Designs Of Multi Ported Memory On Fpga View Details
2 TVREFE19_68 A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA View Details
3 TVREFE19_58 A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA View Details
4 TVREFE19_61 Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA View Details
Front End Research Projects
Sl.No Project ID
QCA nano Technology Projects
Action
1 TVREFE19_06 Design Of Majority Logic (ML) Based Approximate Full Adders View Details
2 TVREFE19_44 Design Of An Efficient Multilayer Arithmetic Logic Unit In Quantum-dot Cellular Automata (QCA) View Details
3 TVREFE19_52 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
Front End Research Projects
Sl.No Project ID
Cadence Oriented Projects
Action
1 TVREFE19_10 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
2 TVREFE19_39 A Parallel Radix-2k FFT Processor Using Single-port Merged-bank Memory View Details
3 TVREFE19_43 Area delay and energy Efficient VLSI Architecture For Scalable In-place Computation of FFT on Real Data View Details
4 TVREFE19_28 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
5 TVREFE19_12 Low-power Approximate Unsigned Multipliers With Configurable Error Recovery View Details
6 TVREFE19_62 Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA View Details
7 TVREFE19_37 A Division-free Toom-cook Multiplication Based Montgomery Modular Multiplication View Details
8 TVREFE19_69 A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA View Details
9 TVREFE19_59 A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA View Details
Front End Research Projects
Sl.No Project ID
Matlab Applications Projects
Action
1 TVREFE19_70 Hardware Co-Simulation of Adaptive Noise Cancellation System using LMS and Leaky LMS Algorithms View Details
2 TVREFE19_63 Design of visible light communication with DCT and M-Ary PAM in Xilinx System Generator View Details
3 TVREFE19_64 XSG-Based control scheme for a grid-connected hybrid generation system View Details
4 TVREFE19_66 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
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