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Sl.No Project ID Communications Projects Action
1 TVMAFE05 A Double Error Correction Code For 32-bit Data Words With Efficient Decoding View Details
2 TVMAFE15 A Probabilistic Parallel Bit-flipping Decoder For Low-density Parity-check Codes View Details
3 TVMAFE17 Error Detection And Correction In SRAM Emulated TCAMs View Details
4 TVMAFE58 Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field View Details
5 TVMAFE59 A New Logic For Implementation Of Digital Error Correction Block View Details
6 TVMAFE72 Low Power Karnaugh Map Approximate Adder For Error Compensation In Loop Accumulations View Details
7 TVMAFE76 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
8 TVMAFE82 Hardware Software Co-simulation of Obfuscated 128-bit AES Algorithm for Image Processing Applications View Details
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