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Sl.No Project Code Arithmetic Core Projects Action
1 TVMAFE01 A Low-power High-speed Accuracy-controllable Approximate Multiplier Design View Details
2 TVMAFE02 Design And Evaluation Of Approximate Logarithmic Multipliers For Low Power Error-tolerant Applications View Details
3 TVREFE19_01 Design And Evaluation Of Approximate Logarithmic Multipliers For Low Power Error-tolerant Applications View Details
4 TVREFE19_07 Design Of Approximate Radix-4 Booth Multipliers For Error-tolerant Computing View Details
5 TVMAFE09 Dual-quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers View Details
6 TVMAFE11 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
7 TVREFE19_09 A Two-speed, Radix-4, Serial–parallel Multiplier View Details
8 TVREFE19_11 Low-power Approximate Unsigned Multipliers With Configurable Error Recovery View Details
9 TVMAFE14 Tosam: An Energy-efficient Truncation- And Rounding-based Scalable Approximate Multiplier View Details
10 TVREFE19_15 Tosam: An Energy-efficient Truncation- And Rounding-based Scalable Approximate Multiplier View Details
11 TVMAFE16 Analysis, Modeling And Optimization Of Equal Segment Based Approximate Adders View Details
12 TVREFE19_17 Analysis, Modeling And Optimization Of Equal Segment Based Approximate Adders View Details
13 TVREFE19_18 Block-based Carry Speculative Approximate Adder For Energy-efficient Applications View Details
14 TVMAFE18 Efficient Implementations Of Reduced Precision Redundancy (RPR) Multiply And Accumulate (MAC) View Details
15 TVMAFE20 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
16 TVMAFE21 A Combined Arithmetic-high-level Synthesis Solution To Deploy Partial Carry-save Radix-8 Booth Multipliers In Datapaths View Details
17 TVREFE19_21 A Combined Arithmetic-high-level Synthesis Solution To Deploy Partial Carry-save Radix-8 Booth Multipliers In Datapaths View Details
18 TVMAFE24 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
19 TVREFE19_24 A Theoretical Framework For Quality Estimation And Optimization Of DSP Applications Using Low-power Approximate Adders View Details
20 TVMAFE25 Concurrent Error Detectable Carry Select Adder With Easy Testability View Details
21 TVMAFE26 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
22 TVREFE19_25 Design And Analysis Of Approximate Redundant Binary Multipliers View Details
23 TVREFE19_26 Digit-serial Versatile Multiplier Based On A Novel Block Recombination Of The Modified Overlap-free Karatsuba Algorithm View Details
24 TVMAFE27 Design Methodology To Explore Hybrid Approximate Adders For Energy-efficient Image And Video Processing Accelerators View Details
25 TVREFE19_29 Design Of Fsm-based Function With Reduced Number Of States In Integral Stochastic Computing View Details
26 TVMAFE28 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
27 TVREFE19_30 Static Delay Variation Models For Ripple-carry And Borrow-save Adders View Details
28 TVMAFE30 Tunable Floating-point Adder View Details
29 TVMAFE32 Low-power High-accuracy Approximate Multiplier Using Approximate High- Order Compressors View Details
30 TVMAFE33 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
31 TVREFE19_31 Machine Learning Based Power Efficient Approximate 4:2 Compressors For Imprecise Multipliers View Details
32 TVMAFE34 Modified Binary Multiplier Circuit Based On Vedic Mathematics View Details
33 TVMIFE01 Performance Analysis Of Wallace Tree Multiplier With Kogge Stone Adder Using 15-4 Compressor View Details
34 TVMAFE35 Rounding Technique Analysis For Power-area & Energy Efficient Approximate Multiplier Design View Details
35 TVREFE19_36 A Division-free Toom-cook Multiplication Based Montgomery Modular Multiplication View Details
36 TVMAFE42 Fast Hub Floating-point Adder For FPGA View Details
37 TVREFE19_48 Fast Hub Floating-point Adder For FPGA View Details
38 TVMAFE43 New Majority Gate Based Parallel BCD Adder Designs For Quantum-dot Cellular Automata View Details
39 TVMAFE50 16 Bit Power Efficient Carry Select Adder View Details
40 TVMAFE52 An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics View Details
41 TVMAFE53 A Design And Implementation Of Montgomery Modular Multiplier View Details
42 TVMAFE56 A Hardware-efficient Logarithmic Multiplier With Improved Accuracy View Details
43 TVMAFE57 A Low Power Binary Square Rooter Using Reversible Logic View Details
44 TVMAFE60 Fast & Energy Efficient Binary To BCD Converter With Complement Based Logic Design (CBLD) For BCD Multipliers View Details
45 TVMAFE63 Design Of Delay Efficient Hybrid Adder For High Speed Applications View Details
46 TVMAFE64 Energy Efficient Speed-independent 64-bit Fused Multiply-add Unit* View Details
47 TVMAFE65 Factorized Carry Look Ahead Adder View Details
48 TVMAFE68 Performance Evaluation Of Fixed-point Array Multipliers On Xilinx FPGAs View Details
49 TVMAFE71 Implementation Of Addition And Subtraction Operations In Multiple Precision Arithmetic View Details
50 TVMAFE75 Sensor-based Approximate Adder Design For Accelerating Error-tolerant And Deep-learning Applications View Details
51 TVREFE19_67 A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA View Details
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