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Sl.No Project ID Transistor Logic Projects Action
1 TVMABE01 Design Of Area-efficient And Highly Reliable Rhbd 10t Memory Cell For Aerospace Applications View Details
2 TVMABE03 Low-power And Fast Full Adder By Exploring New XOR And XNOR Gates View Details
3 TVREBE19_08 Radiation-hardened 14t SRAM Bitcell With Speed And Power Optimized For Space Application View Details
4 TVMABE05 A Very Compact CMOS Analog Multiplier For Application In CNN Synapses View Details
5 TVMABE07 Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique For On-chip Digital Filter Applications View Details
6 TVREBE19_10 Counter Based Low Power, Low Latency Wallace Tree Multiplier Using GDI Technique For On-chip Digital Filter Applications View Details
7 TVMABE09 Design Of Area Efficient And Low Power 4-bit Multiplier Based On Full- Swing GDI Technique View Details
8 TVMABE10 Designing Efficient Circuits Based On Runtime-reconfigurable Field-effect Transistors View Details
9 TVREBE19_11 Designing Efficient Circuits Based On Runtime-reconfigurable Field-effect Transistors View Details
10 TVREBE19_14 Design And Characterization Of SEU Hardened Circuits For SRAM-based FPGA View Details
11 TVREBE19_15 Low Leakage Clock Tree With Dual-threshold- Voltage Split Input–output Repeaters View Details
12 TVMABE14 Parametric And Functional Degradation Analysis Of Complete 14-nm FinFET SRAM View Details
13 TVREBE19_17 Parametric And Functional Degradation Analysis Of Complete 14-nm FinFET SRAM View Details
14 TVMABE18 A 7t Security Oriented SRAM Bitcell View Details
15 TVREBE19_23 A 7t Security Oriented SRAM Bitcell View Details
16 TVREBE19_26 A Low Power And High Speed Voltage Level Shifter Based On A Regulated Cross Coupled Pull Up Network View Details
17 TVMABE19 Energy Efficient Single-ended 6T SRAM For Multimedia Applications View Details
18 TVREBE19_29 Hybrid Logical Effort For Hybrid Logic Style Full Adders In Multistage Structures View Details
19 TVMABE20 Hybrid Logical Effort For Hybrid Logic Style Full Adders In Multistage Structures View Details
20 TVMABE25 Analysis Of 1- Bit Full Adder Using Different Techniques In Cadence 45nm Technology View Details
21 TVMABE26 Seda - Single Exact Dual Approximate Adders For Approximate Processors View Details
22 TVMABE28 Analysis Of Adiabatic Flip-flops For Ultra Low Power Applications View Details
23 TVMABE30 Power-delay-product, Area And Threshold-loss Analysis Of CMOS Full Adder Circuits View Details
24 TVMABE33 Power Reduction In Domino Logic Using Clock Gating In 16nm CMOS Technology View Details
25 TVMABE37 Power Efficient Design Of Adiabatic Approach For Low Power VLSI Circuits View Details
26 TVMABE39 Low Power Approximate Unsigned Divider Design Using Gate Diffusion Input Logic View Details
27 TVMABE41 Design Of Swing Dependent XOR-XNOR Gates Based Hybrid Full Adder View Details
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