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A Solution For Ultra-low Bit-error-rate Interface Of Superconductor-semiconductor By Using An Error-correction-code Encoder

A SOLUTION FOR ULTRA-LOW BIT-ERROR-RATE INTERFACE OF SUPERCONDUCTOR-SEMICONDUCTOR BY USING AN ERROR-CORRECTION-CODE ENCODER

  • Project Code :
  • TVREFE19_40
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A SOLUTION FOR ULTRA-LOW BIT-ERROR-RATE INTERFACE OF SUPERCONDUCTOR-SEMICONDUCTOR BY USING AN ERROR-CORRECTION-CODE ENCODER

This paper introduces a solution for ultra-low biterror- rate interface of superconductor-semiconductor. By using an error-correction-code encoder, the low bit-error-rate requirement could be relaxed considerably. The encoder in our research encodes 32-bit original data with six extra check bits that are generated based on the theory of linear block code to correct 1-bit error. The numerical analysis shows the biasmargin of BER<1010 expands more than 50% for a reported typical interface. Besides, the mean time between failure of the 32-bit interface running at 5 Gbps with 1012 BER improves from 6.25 s to 44 000 years, and the BER requirement for 1 h operation without error is relaxed from 1.7 × 1015 to 1.14 × 108. The implementation uses an optimized 9-stage pipelined structure achieving low latency and high throughput. This encoder is simulated in logic-gate-level and we implemented a virtual SFQ logic which performs pulse clocked logic on a realistic field-programming-gate-array to verify the design.

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