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Design And Characterization Of SEU Hardened Circuits For SRAM-based FPGA

DESIGN AND CHARACTERIZATION OF SEU HARDENED CIRCUITS FOR SRAM-BASED FPGA

  • Project Code :
  • TVREBE19_12
  • .
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DESIGN AND CHARACTERIZATION OF SEU HARDENED CIRCUITS FOR SRAM-BASED FPGA

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration randomaccess memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13-μm CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three
orders of magnitude. On the conditions of linear energy transfer being up to 14MeV·cm2/mg, no SEU errors were observed from DFF in the hardened FPGA design.

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